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https://github.com/espressif/esp-idf.git
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e0bedd19ab
- to acknowledge the unused DCACHE added to DRAM for ESP32-S3 - For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB (from 0x3C000000). - But, if we try allocating memory from the 16 kB block and run an `esp_ptr_internal` check on that memory pointer, it fails as the address block from 0x3C000000 corresponds to the external memory symbols SOC_DROM_LOW and SOC_EXTRAM_DATA_LOW. (E.g. freertos - If the IDLE task stack buffer gets allocated from this region, the firmware will abort due to this failure). - Thus, the checks `esp_ptr_internal`, `esp_ptr_in_drom` and `esp_ptr_byte_accessible` have been updated to acknowledge this memory as a part of the DRAM. Co-authored-by: Mahavir Jain <mahavir@espressif.com>
77 lines
2.1 KiB
C
77 lines
2.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/soc_caps.h"
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#include "esp_attr.h"
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#include "esp_memory_utils.h"
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#if CONFIG_SPIRAM
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#include "esp_private/esp_psram_extram.h"
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#endif
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bool esp_ptr_dma_ext_capable(const void *p)
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{
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#if !SOC_PSRAM_DMA_CAPABLE
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return false;
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#endif //!SOC_PSRAM_DMA_CAPABLE
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#if CONFIG_SPIRAM
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return esp_psram_check_ptr_addr(p);
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#else
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return false;
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#endif //CONFIG_SPIRAM
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}
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bool esp_ptr_byte_accessible(const void *p)
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{
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intptr_t ip = (intptr_t) p;
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bool r;
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r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH);
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#if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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/* For ESP32 case, RTC fast memory is accessible to PRO cpu only and hence
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* for single core configuration (where it gets added to system heap) following
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* additional check is required */
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r |= (ip >= SOC_RTC_DRAM_LOW && ip < SOC_RTC_DRAM_HIGH);
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#endif
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#if CONFIG_SPIRAM
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r |= esp_psram_check_ptr_addr(p);
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#endif
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#if CONFIG_ESP32S3_DATA_CACHE_16KB
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/* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is
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* added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB
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* (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000).
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* Though this memory lies in the external memory vaddr, it is no different
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* from the internal RAM in terms of hardware attributes. It is a part of
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* the internal RAM when added to the heap and is byte-accessible .*/
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r |= (ip >= SOC_DROM_LOW && ip < (SOC_DROM_LOW + 0x4000));
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#endif
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return r;
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}
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bool esp_ptr_external_ram(const void *p)
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{
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#if !SOC_SPIRAM_SUPPORTED
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return false;
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#endif //!SOC_SPIRAM_SUPPORTED
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#if CONFIG_SPIRAM
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return esp_psram_check_ptr_addr(p);
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#else
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return false;
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#endif //CONFIG_SPIRAM
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}
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#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
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bool esp_stack_ptr_in_extram(uint32_t sp)
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{
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//Check if stack ptr is on PSRAM, and 16 byte aligned.
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return (esp_psram_check_ptr_addr((void *)sp) && ((sp & 0xF) == 0));
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}
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#endif
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