Armando c331c85318 mspi: make cpu clock source switch safe ... For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required. Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be cleared. When system clock switches up, the delays should be restored.		2021-10-19 21:47:27 +08:00
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bootloader_sections	efuse: Burn operation does not block reading	2021-06-18 11:52:47 +08:00
build_test	esp_phy: rename esp_phy component prefix	2021-10-13 13:10:49 +08:00
cxx_no_except	[C++]: wrapper functions around unwind code	2021-04-20 14:27:58 +08:00
flash_psram	mspi: make cpu clock source switch safe	2021-10-19 21:47:27 +08:00
gdb_loadable_elf	tests: gdb_loadable_elf: adjust the breakpoint location for ESP32 ECO3	2021-05-04 16:22:50 +02:00
longjmp_test	[examples]: removed hyphens	2021-10-09 13:58:24 +08:00
memprot	example_tests: Deletes usage esp32c3 ECO0 in CI (by default ECO3)	2021-09-24 13:55:07 +08:00
monitor_ide_integration	fix(test_apps): add supported targets for memprot, panic, monitor_ide	2021-01-27 12:35:49 +08:00
no_embedded_paths	Support ESP32S3 Beta 3 target	2021-03-18 10:24:22 +08:00
panic	Update tests for assert and abort	2021-08-05 11:09:22 +05:30
startup	efuse: Burn operation does not block reading	2021-06-18 11:52:47 +08:00