mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
4df3ff619e
- add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
226 lines
9.9 KiB
C
226 lines
9.9 KiB
C
/**
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
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* core0 monitor enable configuration register
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*/
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#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [0]; default: 0;
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* enbale sp underlow monitor
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(0))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 0
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [1]; default: 0;
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* enbale sp overflow monitor
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(1))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 1
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/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
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* core0 monitor interrupt status register
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*/
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#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [0]; default: 0;
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* sp underlow monitor interrupt status register
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(0))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 0
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [1]; default: 0;
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* sp overflow monitor interupt status register
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(1))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 1
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/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
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* core0 monitor interrupt enable register
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*/
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#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [0]; default: 0;
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* enbale sp underlow monitor interrupt
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(0))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 0
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [1]; default: 0;
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* enbale sp overflow monitor interrupt
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(1))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 1
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/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
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* core0 monitor interrupt clr register
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*/
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#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [0]; default: 0;
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* clr sp underlow monitor interrupt
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(0))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 0
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [1]; default: 0;
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* clr sp overflow monitor interrupt
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(1))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 1
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/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
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* stack min value
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*/
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#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
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/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
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* core0 sp region configuration regsiter
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*/
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#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
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#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
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/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
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* stack max value
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*/
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#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
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/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
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* core0 sp pc status register
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*/
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#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
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#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
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/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
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* stack monitor pc status register
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*/
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#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
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/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
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* This regsiter stores the PC when trigger stack monitor.
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*/
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#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
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#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
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/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
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* record enable configuration register
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*/
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#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
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/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
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* Set 1 to enable record PC
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*/
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#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
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#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
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#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
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/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
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* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
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*/
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
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/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
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* record status regsiter
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*/
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
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/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
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* recorded PC
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*/
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
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/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
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* record status regsiter
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*/
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
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/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
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* recorded sp
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*/
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
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/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
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* cpu status register
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*/
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#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
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/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
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* cpu's lastpc before exception
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*/
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#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
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#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
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/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
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* cpu status register
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*/
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
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/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
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* cpu debug mode status, 1 means cpu enter debug mode.
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*/
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
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/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
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* cpu debug_module active status
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*/
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
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/** ASSIST_DEBUG_CLOCK_GATE_REG register
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* clock gate register
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*/
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#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
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/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
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* clock gate register
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*/
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#define ASSIST_DEBUG_CLK_EN (BIT(0))
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#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
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#define ASSIST_DEBUG_CLK_EN_V 0x00000001U
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#define ASSIST_DEBUG_CLK_EN_S 0
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/** ASSIST_DEBUG_DATE_REG register
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* version register
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*/
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#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1fc)
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/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34627616;
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* version register
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*/
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#define ASSIST_DEBUG_DATE 0x0FFFFFFFU
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#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
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#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU
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#define ASSIST_DEBUG_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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