Omar Chebib a8b1475fe7 feat(riscv): implement coprocessors save area and FPU support ... This commit mainly targets the ESP32-P4. It adds supports for coprocessors on RISC-V based targets. The coprocessor save area, describing the used coprocessors is stored at the end of the stack of each task (highest address) whereas each coprocessor save area is allocated at the beginning of the task (lowest address). The context of each coprocessor is saved lazily, by the task that want to use it.		2023-10-23 11:10:28 +08:00
..
csr.h	bugfix: fix pmp retention and add pma retention	2023-05-29 16:35:03 +08:00
encoding.h	riscv: Add new arch-level component	2020-11-12 09:33:18 +11:00
instruction_decode.h	interrupt: filter out reserved int number by decoding risc-v JAL instruction	2021-01-05 15:39:46 +08:00
interrupt.h	fix(esp32p4): Fixed interrupt handling to use the CLIC controller	2023-08-31 12:16:08 +08:00
rv_utils.h	feat(riscv): implement coprocessors save area and FPU support	2023-10-23 11:10:28 +08:00
rvruntime-frames.h	feat(riscv): implement coprocessors save area and FPU support	2023-10-23 11:10:28 +08:00
rvsleep-frames.h	bugfix: fix pmp retention and add pma retention	2023-05-29 16:35:03 +08:00
semihosting.h	semihosting: version 2	2022-05-05 09:12:42 +00:00