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37fad48e1f
esp-idf/components/ulp/ulp_riscv
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LonerDan 37fad48e1f fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V 
According to the ESP32-S2/S3 TRM, the output pin's mode is set in the RTC_GPIO_PINn_REG
by programming the RTC_GPIO_PINn_PAD_DRIVER bit. The current ULP RISC-V RTCIO driver
however, incorrectly programs the RTC_IO_TOUCH_PADn_REG register field RTC_IO_TOUCH_PADn_DRV.
This commit fixes the bug.
2024-06-18 14:33:13 +02:00
..
include fix(ulp): enable astyle linter and format ULP component 2024-01-22 11:43:38 +08:00
shared/include ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP. 2022-08-05 18:16:31 +08:00
ulp_core fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V 2024-06-18 14:33:13 +02:00
ulp_riscv_i2c.c fix(ulp_riscv): Updated RTC I2C to use open-drain IOs 2024-01-30 14:54:45 +01:00
ulp_riscv_lock.c ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP. 2022-08-05 18:16:31 +08:00
ulp_riscv.c fix(ulp): enable astyle linter and format ULP component 2024-01-22 11:43:38 +08:00