LonerDan 37fad48e1f fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V ... According to the ESP32-S2/S3 TRM, the output pin's mode is set in the RTC_GPIO_PINn_REG by programming the RTC_GPIO_PINn_PAD_DRIVER bit. The current ULP RISC-V RTCIO driver however, incorrectly programs the RTC_IO_TOUCH_PADn_REG register field RTC_IO_TOUCH_PADn_DRV. This commit fixes the bug.		2024-06-18 14:33:13 +02:00
..
cmake	feat(ulp): add lp core panic handler	2024-05-28 14:42:59 +08:00
ld	fix(rtc_memory): fix conflict between LP-ROM and RTC reserved	2024-04-17 13:37:56 +08:00
lp_core	fix(esp_driver_gpio): manage lp_io module clock by driver	2024-06-05 17:56:37 +08:00
test_apps	fix(esp_driver_gpio): manage lp_io module clock by driver	2024-06-05 17:56:37 +08:00
ulp_common	feat(ulp): add basic support for running lp core on C5	2024-03-13 17:37:29 +08:00
ulp_fsm	fix(ulp): enable astyle linter and format ULP component	2024-01-22 11:43:38 +08:00
ulp_riscv	fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V	2024-06-18 14:33:13 +02:00
CMakeLists.txt	ci(doc): enable doc build for esp32c5	2024-04-18 19:39:29 +08:00
component_ulp_common.cmake	ulp: added basic support for building and running a binary in the lp core	2023-03-09 10:12:23 +08:00
esp32ulp_mapgen.py	ulp: esp32ulp_mapgen: remove the special case for RISC-V, cleanup	2022-08-30 02:34:28 +02:00
Kconfig	feat(ulp): add lp core panic handler	2024-05-28 14:42:59 +08:00
project_include.cmake	feat(ulp): Generate compile_commands.json for ulp targets	2024-06-12 10:17:16 +02:00
sdkconfig.rename.esp32	soc: moved kconfig options out of the target component.	2022-04-21 12:09:43 +08:00
sdkconfig.rename.esp32s2	soc: moved kconfig options out of the target component.	2022-04-21 12:09:43 +08:00