mirror of
https://github.com/espressif/esp-idf.git
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68 lines
2.5 KiB
C
68 lines
2.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/efuse_periph.h"
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#include "soc/rtc_cntl_reg.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "soc/dport_reg.h"
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#endif
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#include "esp_rom_sys.h"
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#include "esp_rom_uart.h"
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__attribute__((weak)) void bootloader_clock_configure(void)
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{
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// ROM bootloader may have put a lot of text into UART0 FIFO.
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// Wait for it to be printed.
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// This is not needed on power on reset, when ROM bootloader is running at
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// 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
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// and will be done with the bootloader much earlier than UART FIFO is empty.
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esp_rom_uart_tx_wait_idle(0);
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/* Set CPU to 80MHz. Keep other clocks unmodified. */
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int cpu_freq_mhz = 80;
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#if CONFIG_IDF_TARGET_ESP32
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/* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
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* 240 MHz may cause the chip to lock up (see section 3.5 of the errata
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* document). For rev. 0, switch to 240 instead if it has been enabled
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* previously.
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*/
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uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
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if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
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DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) {
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cpu_freq_mhz = 240;
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}
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#endif
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if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || esp_rom_get_reset_reason(0) != RESET_REASON_CPU0_SW) {
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rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
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#if CONFIG_IDF_TARGET_ESP32
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clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
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#endif
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/* ESP32-S2 doesn't have XTAL_FREQ choice, always 40MHz */
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clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
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clk_cfg.slow_freq = rtc_clk_slow_freq_get();
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clk_cfg.fast_freq = rtc_clk_fast_freq_get();
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rtc_clk_init(clk_cfg);
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}
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/* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
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* it here. Usually it needs some time to start up, so we amortize at least
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* part of the start up time by enabling 32k XTAL early.
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* App startup code will wait until the oscillator has started up.
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*/
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#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
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if (!rtc_clk_32k_enabled()) {
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rtc_clk_32k_bootstrap(CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES);
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}
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#endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
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REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
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}
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