esp-idf

mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00

History

Omar Chebib 5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer G0 doesn't depend on any G1+ layer for RISC-V based targets		2022-06-14 15:00:53 +08:00
..
esp32	Merge branch 'refactor/mcpwm_hal_driver_doc' into 'master'	2022-06-10 10:28:59 +08:00
esp32c2	G0: RISC-V targets have now an independent G0 layer	2022-06-14 15:00:53 +08:00
esp32c3	G0: RISC-V targets have now an independent G0 layer	2022-06-14 15:00:53 +08:00
esp32h2	G0: RISC-V targets have now an independent G0 layer	2022-06-14 15:00:53 +08:00
esp32s2	Merge branch 'feature/efuse_rst_is_treated_as_poweron_rst' into 'master'	2022-06-13 21:26:13 +08:00
esp32s3	Merge branch 'refactor/mcpwm_hal_driver_doc' into 'master'	2022-06-10 10:28:59 +08:00
include/soc	mcpwm: clean up hal driver and add doc	2022-06-02 15:01:18 +08:00
linux/include/soc	build-system: include soc_caps defines into kconfig	2021-12-06 12:37:07 +08:00
CMakeLists.txt	dport: Move DPORT workaround to G0	2022-05-31 13:44:18 +08:00
dport_access_common.c	dport: Move DPORT workaround to G0	2022-05-31 13:44:18 +08:00
linker.lf	soc: move implementations to esp_hw_support	2020-10-28 22:38:50 +08:00
lldesc.c	crypto: initial S3 Beta 3 bringup and testing for SHA/AES/RSA/flash enc	2021-05-18 11:25:41 +08:00
README.md	soc: descriptive part occupy whole component	2020-10-28 07:21:29 +08:00

README.md

`soc`

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware