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2ed15d8b1e
esp-idf/components/soc
History
Sudeep Mohanty 2ed15d8b1e ulp: Added ULP RISC-V support for esp32s3 
This commit adds support for ULP RISC-V for esp32s3.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
2022-01-18 10:58:00 +05:30
..
esp32 spi: support spi on 8684 2022-01-12 11:30:29 +08:00
esp32c3 soc: move peripheral base address into reg_base.h 2022-01-06 21:43:12 +08:00
esp32h2 esp32h2: fix apb freq bug 2022-01-10 12:43:31 +08:00
esp32s2 spi: support spi on 8684 2022-01-12 11:30:29 +08:00
esp32s3 ulp: Added ULP RISC-V support for esp32s3 2022-01-18 10:58:00 +05:30
esp8684 soc: move peripheral base address into reg_base.h 2022-01-06 21:43:12 +08:00
include/soc gpio: remove legacy rtc_io description for esp32 2022-01-06 21:43:12 +08:00
linux/include/soc build-system: include soc_caps defines into kconfig 2021-12-06 12:37:07 +08:00
CMakeLists.txt soc: move peripheral base address into reg_base.h 2022-01-06 21:43:12 +08:00
linker.lf soc: move implementations to esp_hw_support 2020-10-28 22:38:50 +08:00
lldesc.c crypto: initial S3 Beta 3 bringup and testing for SHA/AES/RSA/flash enc 2021-05-18 11:25:41 +08:00
README.md soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00

README.md

soc

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware