mirror of
https://github.com/espressif/esp-idf.git
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fad639f0d4
1. use spi functions in rom 2. remove unnecessary GPIO configurations. 3. remove unnecessary dummy settings. 4. enable dummy out function 5. flash and psram have independent timing setting registers. 6. no need to set 1.9v for LDO in 80Mhz 7. set IO driver ability to 1 by default. 8. no need to use GPIO matrix on esp32s2, IO MUX is recommended 9. enable spi clock mode and IO mode settings
570 lines
24 KiB
Plaintext
570 lines
24 KiB
Plaintext
menu "ESP32S2-specific"
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# TODO: this component simply shouldn't be included
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# in the build at the CMake level, but this is currently
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# not working so we just hide all items here
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visible if IDF_TARGET_ESP32S2BETA
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choice ESP32S2_BETA_CHIP_VERSION
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# TODO: remove once final S2 chip is supported
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prompt "ESP32-S2 Beta chip version"
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default ESP32S2_BETA_VERSION_A
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help
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There are three versions of ESP32-S2 beta chip with different Wi-Fi PHY: A, B and Marlin3.
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This setting must match the chip for Wi-Fi to work correctly. You can determine
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the chip version by reading the markings on top of the chip. It will be one of the
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three options given here.
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The Wi-Fi performance of Marlin3 is the best among the three versions of chip.
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config ESP32S2_BETA_VERSION_A
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bool "Chip7.2.2-A"
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config ESP32S2_BETA_VERSION_B
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bool "Chip7.2.2-B"
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config ESP32S2_BETA_VERSION_MARLIN3
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bool "Marlin3-B2 or Marlin3-B3"
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endchoice
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choice ESP32S2_DEFAULT_CPU_FREQ_MHZ
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prompt "CPU frequency"
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default ESP32S2_DEFAULT_CPU_FREQ_160 if !IDF_ENV_FPGA
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default ESP32S2_DEFAULT_CPU_FREQ_FPGA if IDF_ENV_FPGA
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help
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CPU frequency to be set on application startup.
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config ESP32S2_DEFAULT_CPU_FREQ_FPGA
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bool "FPGA"
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config ESP32S2_DEFAULT_CPU_FREQ_80
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bool "80 MHz"
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config ESP32S2_DEFAULT_CPU_FREQ_160
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bool "160 MHz"
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config ESP32S2_DEFAULT_CPU_FREQ_240
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bool "240 MHz"
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endchoice
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config ESP32S2_DEFAULT_CPU_FREQ_MHZ
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int
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default 40 if IDF_ENV_FPGA
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default 80 if ESP32S2_DEFAULT_CPU_FREQ_80
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default 160 if ESP32S2_DEFAULT_CPU_FREQ_160
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default 240 if ESP32S2_DEFAULT_CPU_FREQ_240
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menu "Cache config"
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choice ESP32S2_INSTRUCTION_CACHE_SIZE
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prompt "Instruction cache size"
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default ESP32S2_INSTRUCTION_CACHE_8KB
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help
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Instruction cache size to be set on application startup.
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If you use 8KB instruction cache rather than 16KB instruction cache,
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then the other 8KB will be added to the heap.
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config ESP32S2_INSTRUCTION_CACHE_8KB
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bool "8KB"
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config ESP32S2_INSTRUCTION_CACHE_16KB
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bool "16KB"
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endchoice
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choice ESP32S2_INSTRUCTION_CACHE_LINE_SIZE
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prompt "Instruction cache line size"
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default ESP32S2_INSTRUCTION_CACHE_LINE_32B
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help
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Instruction cache line size to be set on application startup.
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config ESP32S2_INSTRUCTION_CACHE_LINE_16B
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bool "16 Bytes"
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config ESP32S2_INSTRUCTION_CACHE_LINE_32B
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bool "32 Bytes"
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endchoice
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choice ESP32S2_DATA_CACHE_SIZE
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prompt "Data cache size"
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default ESP32S2_DATA_CACHE_8KB
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help
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Data cache size to be set on application startup.
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If you use 8KB data cache rather than 16KB data cache, the other 8KB will be added to the heap.
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config ESP32S2_DATA_CACHE_0KB
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depends on !ESP32S2_SPIRAM_SUPPORT
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bool "0KB"
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config ESP32S2_DATA_CACHE_8KB
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bool "8KB"
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config ESP32S2_DATA_CACHE_16KB
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bool "16KB"
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endchoice
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choice ESP32S2_DATA_CACHE_LINE_SIZE
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prompt "Data cache line size"
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default ESP32S2_DATA_CACHE_LINE_32B
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help
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Data cache line size to be set on application startup.
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config ESP32S2_DATA_CACHE_LINE_16B
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bool "16 Bytes"
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config ESP32S2_DATA_CACHE_LINE_32B
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bool "32 Bytes"
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endchoice
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config ESP32S2_INSTRUCTION_CACHE_WRAP
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bool "Enable instruction cache wrap"
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default "n"
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help
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If enabled, instruction cache will use wrap mode to read spi flash (maybe spiram).
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The wrap length equals to INSTRUCTION_CACHE_LINE_SIZE.
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However, it depends on complex conditions.
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config ESP32S2_DATA_CACHE_WRAP
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bool "Enable data cache wrap"
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default "n"
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help
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If enabled, data cache will use wrap mode to read spiram (maybe spi flash).
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The wrap length equals to DATA_CACHE_LINE_SIZE.
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However, it depends on complex conditions.
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endmenu # Cache config
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# Note: to support SPIRAM across multiple chips, check CONFIG_SPIRAM
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# instead
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config ESP32S2_SPIRAM_SUPPORT
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bool "Support for external, SPI-connected RAM"
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default "n"
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select SPIRAM
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help
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This enables support for an external SPI RAM chip, connected in parallel with the
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main SPI flash chip.
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menu "SPI RAM config"
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depends on ESP32S2_SPIRAM_SUPPORT
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choice SPIRAM_TYPE
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prompt "Type of SPI RAM chip in use"
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default SPIRAM_TYPE_ESPPSRAM32
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config SPIRAM_TYPE_ESPPSRAM32
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bool "ESP-PSRAM32 or IS25WP032"
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config SPIRAM_TYPE_ESPPSRAM64
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bool "ESP-PSRAM64 or LY68L6400"
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endchoice
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config SPIRAM_SIZE
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int
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default 4194304 if SPIRAM_TYPE_ESPPSRAM32
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default 8388608 if SPIRAM_TYPE_ESPPSRAM64
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default 0
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menu "PSRAM clock and cs IO for ESP32S2"
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depends on ESP32S2_SPIRAM_SUPPORT
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config DEFAULT_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 30
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help
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The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design.
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config DEFAULT_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 26
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
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endmenu
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config SPIRAM_SPIWP_SD3_PIN
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int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)"
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depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
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range 0 33
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default 28
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help
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This value is ignored unless flash mode is set to DIO or DOUT and the SPI flash pins have been
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overriden by setting the eFuses SPI_PAD_CONFIG_xxx.
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Different from esp32 chip, on esp32s2, the WP pin would also be defined in efuse. This value would only
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be used if the WP pin recorded in efuse SPI_PAD_CONFIG_xxx is invalid.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set as the value configured in
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bootloader.
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config SPIRAM_FETCH_INSTRUCTIONS
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bool "Cache fetch instructions from SPI RAM"
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default n
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help
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If enabled, instruction in flash will be copied into SPIRAM.
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If SPIRAM_RODATA also enabled,
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you can run the instruction when erasing or programming the flash.
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config SPIRAM_RODATA
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bool "Cache load read only data from SPI RAM"
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default n
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help
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If enabled, radata in flash will be copied into SPIRAM.
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If SPIRAM_FETCH_INSTRUCTIONS also enabled,
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you can run the instruction when erasing or programming the flash.
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config SPIRAM_USE_AHB_DBUS3
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bool "Enable AHB DBUS3 to access SPIRAM"
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default n
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help
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If Enabled, if SPI_CONFIG_SIZE is bigger then 10MB+576KB,
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then you can have 4MB more space to map the SPIRAM.
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However, the AHB bus is slower than other data cache buses.
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choice SPIRAM_SPEED
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prompt "Set RAM clock speed"
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default SPIRAM_SPEED_40M
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help
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Select the speed for the SPI RAM chip.
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If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
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1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz
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2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz
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3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz
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Note: If the third mode(80Mhz+80Mhz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
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will be occupied by the system. Which SPI host to use can be selected by the config item
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SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
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option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
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(ESPTOOLPY_FLASHFREQ_80M is true)
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config SPIRAM_SPEED_80M
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bool "80MHz clock speed"
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config SPIRAM_SPEED_40M
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bool "40Mhz clock speed"
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config SPIRAM_SPEED_26M
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bool "26Mhz clock speed"
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config SPIRAM_SPEED_20M
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bool "20Mhz clock speed"
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endchoice
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# insert non-chip-specific items here
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source "$IDF_PATH/components/esp_common/Kconfig.spiram.common"
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endmenu
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config ESP32S2_MEMMAP_TRACEMEM
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bool
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default "n"
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config ESP32S2_TRAX
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bool "Use TRAX tracing feature"
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default "n"
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select ESP32S2_MEMMAP_TRACEMEM
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help
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The ESP32S2 contains a feature which allows you to trace the execution path the processor
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has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
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of memory that can't be used for general purposes anymore. Disable this if you do not know
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what this is.
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config ESP32S2_TRACEMEM_RESERVE_DRAM
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hex
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default 0x8000 if ESP32S2_MEMMAP_TRACEMEM && ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
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default 0x4000 if ESP32S2_MEMMAP_TRACEMEM && !ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
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default 0x0
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choice ESP32S2_UNIVERSAL_MAC_ADDRESSES
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bool "Number of universally administered (by IEEE) MAC address"
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default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
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help
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Configure the number of universally administered (by IEEE) MAC addresses.
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During initialization, MAC addresses for each network interface are generated or derived from a
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single base MAC address.
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If the number of universal MAC addresses is Two, all interfaces (WiFi station, WiFi softap) receive a
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universally administered MAC address. They are generated sequentially by adding 0, and 1 (respectively)
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to the final octet of the base MAC address. If the number of universal MAC addresses is one,
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only WiFi station receives a universally administered MAC address.
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It's generated by adding 0 to the base MAC address.
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The WiFi softap receives local MAC addresses. It's derived from the universal WiFi station MAC addresses.
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When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
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a custom universal MAC address range, the correct setting will depend on the allocation of MAC
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addresses in this range (either 1 or 2 per device.)
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config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE
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bool "One"
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select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
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config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
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bool "Two"
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select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
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select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
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endchoice
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config ESP32S2_UNIVERSAL_MAC_ADDRESSES
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int
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default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE
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default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
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config ESP32S2_ULP_COPROC_ENABLED
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bool "Enable Ultra Low Power (ULP) Coprocessor"
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default "n"
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help
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Set to 'y' if you plan to load a firmware for the coprocessor.
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If this option is enabled, further coprocessor configuration will appear in the Components menu.
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config ESP32S2_ULP_COPROC_RESERVE_MEM
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int
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prompt "RTC slow memory reserved for coprocessor" if ESP32S2_ULP_COPROC_ENABLED
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default 512 if ESP32S2_ULP_COPROC_ENABLED
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range 32 8192 if ESP32S2_ULP_COPROC_ENABLED
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default 0 if !ESP32S2_ULP_COPROC_ENABLED
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range 0 0 if !ESP32S2_ULP_COPROC_ENABLED
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help
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Bytes of memory to reserve for ULP coprocessor firmware & data.
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Data is reserved at the beginning of RTC slow memory.
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choice ESP32S2_PANIC
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prompt "Panic handler behaviour"
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default ESP32S2_PANIC_PRINT_REBOOT
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help
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If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
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invoked. Configure the panic handlers action here.
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config ESP32S2_PANIC_PRINT_HALT
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bool "Print registers and halt"
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help
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Outputs the relevant registers over the serial port and halt the
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processor. Needs a manual reset to restart.
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config ESP32S2_PANIC_PRINT_REBOOT
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bool "Print registers and reboot"
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help
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Outputs the relevant registers over the serial port and immediately
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reset the processor.
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config ESP32S2_PANIC_SILENT_REBOOT
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bool "Silent reboot"
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help
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Just resets the processor without outputting anything
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config ESP32S2_PANIC_GDBSTUB
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bool "Invoke GDBStub"
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select ESP_GDBSTUB_ENABLED
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help
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Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
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of the crash.
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endchoice
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config ESP32S2_DEBUG_OCDAWARE
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bool "Make exception and panic handlers JTAG/OCD aware"
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default y
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select FREERTOS_DEBUG_OCDAWARE
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help
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The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and
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instead of panicking, have the debugger stop on the offending instruction.
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config ESP32S2_DEBUG_STUBS_ENABLE
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bool "OpenOCD debug stubs"
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default COMPILER_OPTIMIZATION_LEVEL_DEBUG
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depends on !ESP32S2_TRAX
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help
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Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging,
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e.g. GCOV data dump.
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config ESP32S2_BROWNOUT_DET
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bool "Hardware brownout detect & reset"
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default y
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help
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The ESP32S2 has a built-in brownout detector which can detect if the voltage is lower than
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a specific value. If this happens, it will reset the chip in order to prevent unintended
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behaviour.
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choice ESP32S2_BROWNOUT_DET_LVL_SEL
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prompt "Brownout voltage level"
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depends on ESP32S2_BROWNOUT_DET
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default ESP32S2_BROWNOUT_DET_LVL_SEL_0
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help
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The brownout detector will reset the chip when the supply voltage is approximately
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below this level. Note that there may be some variation of brownout voltage level
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between each ESP32 chip.
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#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
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#of the brownout threshold levels.
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config ESP32S2_BROWNOUT_DET_LVL_SEL_0
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bool "2.43V +/- 0.05"
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config ESP32S2_BROWNOUT_DET_LVL_SEL_1
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bool "2.48V +/- 0.05"
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config ESP32S2_BROWNOUT_DET_LVL_SEL_2
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bool "2.58V +/- 0.05"
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config ESP32S2_BROWNOUT_DET_LVL_SEL_3
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bool "2.62V +/- 0.05"
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config ESP32S2_BROWNOUT_DET_LVL_SEL_4
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bool "2.67V +/- 0.05"
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config ESP32S2_BROWNOUT_DET_LVL_SEL_5
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bool "2.70V +/- 0.05"
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config ESP32S2_BROWNOUT_DET_LVL_SEL_6
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bool "2.77V +/- 0.05"
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config ESP32S2_BROWNOUT_DET_LVL_SEL_7
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bool "2.80V +/- 0.05"
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endchoice
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config ESP32S2_BROWNOUT_DET_LVL
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int
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default 0 if ESP32S2_BROWNOUT_DET_LVL_SEL_0
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default 1 if ESP32S2_BROWNOUT_DET_LVL_SEL_1
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default 2 if ESP32S2_BROWNOUT_DET_LVL_SEL_2
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default 3 if ESP32S2_BROWNOUT_DET_LVL_SEL_3
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default 4 if ESP32S2_BROWNOUT_DET_LVL_SEL_4
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default 5 if ESP32S2_BROWNOUT_DET_LVL_SEL_5
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default 6 if ESP32S2_BROWNOUT_DET_LVL_SEL_6
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default 7 if ESP32S2_BROWNOUT_DET_LVL_SEL_7
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# Note about the use of "FRC1" name: currently FRC1 timer is not used for
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# high resolution timekeeping anymore. Instead the esp_timer API, implemented
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# using FRC2 timer, is used.
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# FRC1 name in the option name is kept for compatibility.
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choice ESP32S2_TIME_SYSCALL
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prompt "Timers used for gettimeofday function"
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default ESP32S2_TIME_SYSCALL_USE_RTC_FRC1
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help
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This setting defines which hardware timers are used to
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implement 'gettimeofday' and 'time' functions in C library.
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- If both high-resolution and RTC timers are used, timekeeping will
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continue in deep sleep. Time will be reported at 1 microsecond
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resolution. This is the default, and the recommended option.
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- If only high-resolution timer is used, gettimeofday will
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provide time at microsecond resolution.
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Time will not be preserved when going into deep sleep mode.
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- If only RTC timer is used, timekeeping will continue in
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deep sleep, but time will be measured at 6.(6) microsecond
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resolution. Also the gettimeofday function itself may take
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longer to run.
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- If no timers are used, gettimeofday and time functions
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return -1 and set errno to ENOSYS.
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- When RTC is used for timekeeping, two RTC_STORE registers are
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used to keep time in deep sleep mode.
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config ESP32S2_TIME_SYSCALL_USE_RTC_FRC1
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bool "RTC and high-resolution timer"
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config ESP32S2_TIME_SYSCALL_USE_RTC
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bool "RTC"
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config ESP32S2_TIME_SYSCALL_USE_FRC1
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bool "High-resolution timer"
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config ESP32S2_TIME_SYSCALL_USE_NONE
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bool "None"
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endchoice
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choice ESP32S2_RTC_CLK_SRC
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prompt "RTC clock source"
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default ESP32S2_RTC_CLK_SRC_INT_RC
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help
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Choose which clock is used as RTC clock source.
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config ESP32S2_RTC_CLK_SRC_INT_RC
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bool "Internal 150kHz RC oscillator"
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config ESP32S2_RTC_CLK_SRC_EXT_CRYS
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bool "External 32kHz crystal"
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endchoice
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config ESP32S2_RTC_CLK_CAL_CYCLES
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int "Number of cycles for RTC_SLOW_CLK calibration"
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default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS
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default 1024 if ESP32S2_RTC_CLK_SRC_INT_RC
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range 0 125000
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help
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|
When the startup code initializes RTC_SLOW_CLK, it can perform
|
|
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
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frequency. This option sets the number of RTC_SLOW_CLK cycles measured
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|
by the calibration routine. Higher numbers increase calibration
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|
precision, which may be important for applications which spend a lot of
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time in deep sleep. Lower numbers reduce startup time.
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|
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When this option is set to 0, clock calibration will not be performed at
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|
startup, and approximate clock frequencies will be assumed:
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|
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- 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
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|
- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
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In case more value will help improve the definition of the launch of the crystal.
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|
If the crystal could not start, it will be switched to internal RC.
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|
|
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config ESP32S2_DISABLE_BASIC_ROM_CONSOLE
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|
bool "Permanently disable BASIC ROM Console"
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|
default n
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|
help
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|
If set, the first time the app boots it will disable the BASIC ROM Console
|
|
permanently (by burning an eFuse).
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|
|
|
Otherwise, the BASIC ROM Console starts on reset if no valid bootloader is
|
|
read from the flash.
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|
|
|
(Enabling secure boot also disables the BASIC ROM Console by default.)
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|
|
|
config ESP32S2_NO_BLOBS
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|
bool "No Binary Blobs"
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|
depends on !BT_ENABLED
|
|
default n
|
|
help
|
|
If enabled, this disables the linking of binary libraries in the application build. Note
|
|
that after enabling this Wi-Fi/Bluetooth will not work.
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|
|
|
endmenu # ESP32S2-Specific
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|
|
|
menu "Power Management"
|
|
# TODO: this component simply shouldn't be included
|
|
# in the build at the CMake level, but this is currently
|
|
# not working so we just hide all items here
|
|
visible if IDF_TARGET_ESP32S2BETA
|
|
|
|
config PM_ENABLE
|
|
bool "Support for power management"
|
|
default n
|
|
help
|
|
If enabled, application is compiled with support for power management.
|
|
This option has run-time overhead (increased interrupt latency,
|
|
longer time to enter idle state), and it also reduces accuracy of
|
|
RTOS ticks and timers used for timekeeping.
|
|
Enable this option if application uses power management APIs.
|
|
|
|
config PM_DFS_INIT_AUTO
|
|
bool "Enable dynamic frequency scaling (DFS) at startup"
|
|
depends on PM_ENABLE
|
|
default n
|
|
help
|
|
If enabled, startup code configures dynamic frequency scaling.
|
|
Max CPU frequency is set to CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ setting,
|
|
min frequency is set to XTAL frequency.
|
|
If disabled, DFS will not be active until the application
|
|
configures it using esp_pm_configure function.
|
|
|
|
config PM_USE_RTC_TIMER_REF
|
|
bool "Use RTC timer to prevent time drift (EXPERIMENTAL)"
|
|
depends on PM_ENABLE && (ESP32S2_TIME_SYSCALL_USE_RTC || ESP32S2_TIME_SYSCALL_USE_RTC_FRC1)
|
|
default n
|
|
help
|
|
When APB clock frequency changes, high-resolution timer (esp_timer)
|
|
scale and base value need to be adjusted. Each adjustment may cause
|
|
small error, and over time such small errors may cause time drift.
|
|
If this option is enabled, RTC timer will be used as a reference to
|
|
compensate for the drift.
|
|
It is recommended that this option is only used if 32k XTAL is selected
|
|
as RTC clock source.
|
|
|
|
config PM_PROFILING
|
|
bool "Enable profiling counters for PM locks"
|
|
depends on PM_ENABLE
|
|
default n
|
|
help
|
|
If enabled, esp_pm_* functions will keep track of the amount of time
|
|
each of the power management locks has been held, and esp_pm_dump_locks
|
|
function will print this information.
|
|
This feature can be used to analyze which locks are preventing the chip
|
|
from going into a lower power state, and see what time the chip spends
|
|
in each power saving mode. This feature does incur some run-time
|
|
overhead, so should typically be disabled in production builds.
|
|
|
|
config PM_TRACE
|
|
bool "Enable debug tracing of PM using GPIOs"
|
|
depends on PM_ENABLE
|
|
default n
|
|
help
|
|
If enabled, some GPIOs will be used to signal events such as RTOS ticks,
|
|
frequency switching, entry/exit from idle state. Refer to pm_trace.c
|
|
file for the list of GPIOs.
|
|
This feature is intended to be used when analyzing/debugging behavior
|
|
of power management implementation, and should be kept disabled in
|
|
applications.
|
|
|
|
|
|
endmenu # "Power Management"
|