Omar Chebib 8fae0f0753 G0: Support Xtensa targets for G0-only compilation ... G0-only example now supports Xtensa targets. This means that G0 layer does not depend on G1+ layers anymore		2022-06-20 11:34:20 +00:00
..
private_include	G0: Support Xtensa targets for G0-only compilation	2022-06-20 11:34:20 +00:00
async_memcpy_impl_cp_dma.c	esp_hw_support: update copyright notice 4	2021-08-10 13:31:53 +02:00
chip_info.c	soc: Adds efuse hal	2022-02-24 22:20:09 +08:00
CMakeLists.txt	esp_psram: new psram component	2022-06-14 15:44:27 +08:00
esp_crypto_lock.c	esp32s2, esp32s3: update copyright notice	2021-08-05 15:01:26 +02:00
esp_ds.c	esp32s2, esp32s3: update copyright notice	2021-08-05 15:01:26 +02:00
esp_hmac.c	esp32s2/hmac: Release HMAC lock in downstream mode incase of failure	2021-09-06 11:21:39 +05:30
Kconfig.mac	esp32: move mac target specific configs	2021-03-31 19:17:33 +08:00
Kconfig.rtc	clk_tree: add initial docs for clock tree	2022-05-24 22:59:51 +08:00
memprot.c	dport: Move DPORT workaround to G0	2022-05-31 13:44:18 +08:00
rtc_clk_init.c	rtc_clk: Fix rtc8m calibration failure after cpu/core reset	2022-06-13 17:47:51 +08:00
rtc_clk.c	clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem	2022-06-13 17:47:50 +08:00
rtc_init.c	rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in	2022-05-24 22:59:41 +08:00
rtc_pm.c	rename APB_CTRL ro SYS_CON	2021-09-16 20:57:57 +08:00
rtc_sleep.c	rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in	2022-05-24 22:59:41 +08:00
rtc_time.c	rtc_clk: Fix rtc8m calibration failure after cpu/core reset	2022-06-13 17:47:51 +08:00