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508fb79a26
In some cases, when data was just written into UART FIFO, transmitter state could be still zero while the FIFO did contain some data. This resulted in uart_tx_wait_idle occasionally returning before all the data was sent out. Fix by checking both UART transmitter state and TX FIFO count. |
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.. | ||
aes.h | ||
bigint.h | ||
cache.h | ||
crc.h | ||
efuse.h | ||
ets_sys.h | ||
gpio.h | ||
libc_stubs.h | ||
lldesc.h | ||
md5_hash.h | ||
miniz.h | ||
queue.h | ||
rtc.h | ||
secure_boot.h | ||
sha.h | ||
spi_flash.h | ||
tbconsole.h | ||
tjpgd.h | ||
uart.h |