mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
304 lines
7.2 KiB
C
304 lines
7.2 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configure Register */
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/** Type of i2c0_ctrl register
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* need des
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*/
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typedef union {
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struct {
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/** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
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* need des
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*/
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uint32_t i2c0_ctrl:25;
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/** i2c0_busy : RO; bitpos: [25]; default: 0;
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* need des
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*/
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uint32_t i2c0_busy:1;
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uint32_t reserved_26:6;
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};
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uint32_t val;
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} i2c_ana_mst_i2c0_ctrl_reg_t;
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/** Type of i2c1_ctrl register
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* need des
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*/
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typedef union {
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struct {
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/** i2c1_ctrl : R/W; bitpos: [24:0]; default: 0;
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* need des
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*/
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uint32_t i2c1_ctrl:25;
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/** i2c1_busy : RO; bitpos: [25]; default: 0;
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* need des
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*/
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uint32_t i2c1_busy:1;
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uint32_t reserved_26:6;
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};
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uint32_t val;
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} i2c_ana_mst_i2c1_ctrl_reg_t;
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/** Type of i2c0_conf register
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* need des
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*/
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typedef union {
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struct {
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/** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
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* need des
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*/
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uint32_t i2c0_conf:24;
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/** i2c0_status : RO; bitpos: [31:24]; default: 0;
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* need des
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*/
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uint32_t i2c0_status:8;
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};
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uint32_t val;
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} i2c_ana_mst_i2c0_conf_reg_t;
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/** Type of i2c1_conf register
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* need des
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*/
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typedef union {
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struct {
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/** i2c1_conf : R/W; bitpos: [23:0]; default: 0;
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* need des
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*/
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uint32_t i2c1_conf:24;
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/** i2c1_status : RO; bitpos: [31:24]; default: 0;
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* need des
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*/
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uint32_t i2c1_status:8;
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};
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uint32_t val;
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} i2c_ana_mst_i2c1_conf_reg_t;
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/** Type of i2c_burst_conf register
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* need des
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*/
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typedef union {
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struct {
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/** i2c_mst_burst_ctrl : R/W; bitpos: [31:0]; default: 0;
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* need des
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*/
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uint32_t i2c_mst_burst_ctrl:32;
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};
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uint32_t val;
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} i2c_ana_mst_i2c_burst_conf_reg_t;
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/** Type of i2c_burst_status register
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* need des
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*/
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typedef union {
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struct {
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/** i2c_mst_burst_done : RO; bitpos: [0]; default: 0;
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* need des
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*/
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uint32_t i2c_mst_burst_done:1;
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/** i2c_mst0_burst_err_flag : RO; bitpos: [1]; default: 0;
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* need des
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*/
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uint32_t i2c_mst0_burst_err_flag:1;
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/** i2c_mst1_burst_err_flag : RO; bitpos: [2]; default: 0;
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* need des
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*/
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uint32_t i2c_mst1_burst_err_flag:1;
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uint32_t reserved_3:17;
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/** i2c_mst_burst_timeout_cnt : R/W; bitpos: [31:20]; default: 1024;
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* need des
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*/
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uint32_t i2c_mst_burst_timeout_cnt:12;
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};
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uint32_t val;
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} i2c_ana_mst_i2c_burst_status_reg_t;
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/** Type of ana_conf0 register
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* need des
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*/
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typedef union {
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struct {
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/** ana_conf0 : R/W; bitpos: [23:0]; default: 0;
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* need des
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*/
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uint32_t ana_conf0:24;
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/** ana_status0 : RO; bitpos: [31:24]; default: 0;
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* need des
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*/
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uint32_t ana_status0:8;
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};
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uint32_t val;
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} i2c_ana_mst_ana_conf0_reg_t;
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/** Type of ana_conf1 register
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* need des
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*/
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typedef union {
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struct {
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/** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
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* need des
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*/
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uint32_t ana_conf1:24;
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/** ana_status1 : RO; bitpos: [31:24]; default: 0;
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* need des
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*/
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uint32_t ana_status1:8;
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};
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uint32_t val;
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} i2c_ana_mst_ana_conf1_reg_t;
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/** Type of ana_conf2 register
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* need des
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*/
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typedef union {
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struct {
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/** ana_conf2 : R/W; bitpos: [23:0]; default: 0;
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* need des
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*/
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uint32_t ana_conf2:24;
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/** ana_status2 : RO; bitpos: [31:24]; default: 0;
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* need des
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*/
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uint32_t ana_status2:8;
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};
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uint32_t val;
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} i2c_ana_mst_ana_conf2_reg_t;
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/** Type of i2c0_ctrl1 register
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* need des
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*/
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typedef union {
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struct {
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/** i2c0_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
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* need des
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*/
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uint32_t i2c0_scl_pulse_dur:6;
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/** i2c0_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
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* need des
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*/
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uint32_t i2c0_sda_side_guard:5;
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uint32_t reserved_11:21;
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};
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uint32_t val;
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} i2c_ana_mst_i2c0_ctrl1_reg_t;
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/** Type of i2c1_ctrl1 register
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* need des
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*/
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typedef union {
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struct {
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/** i2c1_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
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* need des
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*/
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uint32_t i2c1_scl_pulse_dur:6;
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/** i2c1_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
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* need des
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*/
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uint32_t i2c1_sda_side_guard:5;
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uint32_t reserved_11:21;
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};
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uint32_t val;
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} i2c_ana_mst_i2c1_ctrl1_reg_t;
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/** Type of hw_i2c_ctrl register
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* need des
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*/
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typedef union {
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struct {
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/** hw_i2c_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
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* need des
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*/
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uint32_t hw_i2c_scl_pulse_dur:6;
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/** hw_i2c_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
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* need des
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*/
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uint32_t hw_i2c_sda_side_guard:5;
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/** arbiter_dis : R/W; bitpos: [11]; default: 0;
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* need des
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*/
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uint32_t arbiter_dis:1;
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uint32_t reserved_12:20;
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};
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uint32_t val;
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} i2c_ana_mst_hw_i2c_ctrl_reg_t;
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/** Type of nouse register
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* need des
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*/
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typedef union {
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struct {
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/** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
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* need des
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*/
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uint32_t i2c_mst_nouse:32;
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};
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uint32_t val;
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} i2c_ana_mst_nouse_reg_t;
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/** Type of clk160m register
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* need des
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*/
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typedef union {
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struct {
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/** clk_i2c_mst_sel_160m : R/W; bitpos: [0]; default: 0;
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* need des
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*/
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uint32_t clk_i2c_mst_sel_160m:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} i2c_ana_mst_clk160m_reg_t;
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/** Type of date register
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* need des
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 35656448;
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* need des
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*/
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uint32_t date:28;
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/** i2c_mst_clk_en : R/W; bitpos: [28]; default: 0;
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* need des
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*/
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uint32_t i2c_mst_clk_en:1;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} i2c_ana_mst_date_reg_t;
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typedef struct {
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volatile i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
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volatile i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl;
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volatile i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
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volatile i2c_ana_mst_i2c1_conf_reg_t i2c1_conf;
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volatile i2c_ana_mst_i2c_burst_conf_reg_t i2c_burst_conf;
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volatile i2c_ana_mst_i2c_burst_status_reg_t i2c_burst_status;
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volatile i2c_ana_mst_ana_conf0_reg_t ana_conf0;
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volatile i2c_ana_mst_ana_conf1_reg_t ana_conf1;
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volatile i2c_ana_mst_ana_conf2_reg_t ana_conf2;
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volatile i2c_ana_mst_i2c0_ctrl1_reg_t i2c0_ctrl1;
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volatile i2c_ana_mst_i2c1_ctrl1_reg_t i2c1_ctrl1;
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volatile i2c_ana_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl;
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volatile i2c_ana_mst_nouse_reg_t nouse;
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volatile i2c_ana_mst_clk160m_reg_t clk160m;
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volatile i2c_ana_mst_date_reg_t date;
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} i2c_ana_mst_dev_t;
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#ifndef __cplusplus
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_Static_assert(sizeof(i2c_ana_mst_dev_t) == 0x3c, "Invalid size of i2c_ana_mst_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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