mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
1317 lines
45 KiB
C
1317 lines
45 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: monitor configuration registers */
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/** Type of core_0_intr_ena register
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* core0 monitor enable configuration register
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*/
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typedef union {
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struct {
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/** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
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* Core0 dram0 area0 read monitor enable
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*/
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uint32_t core_0_area_dram0_0_rd_ena:1;
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/** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
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* Core0 dram0 area0 write monitor enable
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*/
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uint32_t core_0_area_dram0_0_wr_ena:1;
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/** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
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* Core0 dram0 area1 read monitor enable
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*/
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uint32_t core_0_area_dram0_1_rd_ena:1;
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/** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
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* Core0 dram0 area1 write monitor enable
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*/
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uint32_t core_0_area_dram0_1_wr_ena:1;
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/** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
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* Core0 PIF area0 read monitor enable
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*/
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uint32_t core_0_area_pif_0_rd_ena:1;
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/** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
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* Core0 PIF area0 write monitor enable
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*/
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uint32_t core_0_area_pif_0_wr_ena:1;
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/** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
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* Core0 PIF area1 read monitor enable
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*/
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uint32_t core_0_area_pif_1_rd_ena:1;
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/** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
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* Core0 PIF area1 write monitor enable
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*/
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uint32_t core_0_area_pif_1_wr_ena:1;
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/** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
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* Core0 stackpoint underflow monitor enable
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*/
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uint32_t core_0_sp_spill_min_ena:1;
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/** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
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* Core0 stackpoint overflow monitor enable
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*/
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uint32_t core_0_sp_spill_max_ena:1;
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uint32_t reserved_10:22;
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};
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uint32_t val;
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} assist_debug_core_0_intr_ena_reg_t;
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/** Type of core_0_area_dram0_0_min register
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* core0 dram0 region0 addr configuration register
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*/
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typedef union {
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struct {
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/** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
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* Core0 dram0 region0 start addr
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*/
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uint32_t core_0_area_dram0_0_min:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_dram0_0_min_reg_t;
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/** Type of core_0_area_dram0_0_max register
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* core0 dram0 region0 addr configuration register
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*/
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typedef union {
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struct {
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/** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
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* Core0 dram0 region0 end addr
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*/
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uint32_t core_0_area_dram0_0_max:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_dram0_0_max_reg_t;
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/** Type of core_0_area_dram0_1_min register
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* core0 dram0 region1 addr configuration register
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*/
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typedef union {
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struct {
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/** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
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* Core0 dram0 region1 start addr
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*/
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uint32_t core_0_area_dram0_1_min:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_dram0_1_min_reg_t;
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/** Type of core_0_area_dram0_1_max register
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* core0 dram0 region1 addr configuration register
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*/
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typedef union {
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struct {
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/** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
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* Core0 dram0 region1 end addr
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*/
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uint32_t core_0_area_dram0_1_max:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_dram0_1_max_reg_t;
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/** Type of core_0_area_pif_0_min register
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* core0 PIF region0 addr configuration register
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*/
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typedef union {
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struct {
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/** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
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* Core0 PIF region0 start addr
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*/
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uint32_t core_0_area_pif_0_min:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_pif_0_min_reg_t;
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/** Type of core_0_area_pif_0_max register
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* core0 PIF region0 addr configuration register
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*/
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typedef union {
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struct {
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/** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
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* Core0 PIF region0 end addr
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*/
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uint32_t core_0_area_pif_0_max:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_pif_0_max_reg_t;
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/** Type of core_0_area_pif_1_min register
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* core0 PIF region1 addr configuration register
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*/
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typedef union {
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struct {
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/** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
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* Core0 PIF region1 start addr
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*/
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uint32_t core_0_area_pif_1_min:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_pif_1_min_reg_t;
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/** Type of core_0_area_pif_1_max register
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* core0 PIF region1 addr configuration register
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*/
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typedef union {
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struct {
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/** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
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* Core0 PIF region1 end addr
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*/
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uint32_t core_0_area_pif_1_max:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_pif_1_max_reg_t;
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/** Type of core_0_area_pc register
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* core0 area pc status register
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*/
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typedef union {
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struct {
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/** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
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* the stackpointer when first touch region monitor interrupt
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*/
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uint32_t core_0_area_pc:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_pc_reg_t;
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/** Type of core_0_area_sp register
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* core0 area sp status register
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*/
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typedef union {
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struct {
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/** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
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* the PC when first touch region monitor interrupt
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*/
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uint32_t core_0_area_sp:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_sp_reg_t;
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/** Type of core_0_sp_min register
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* stack min value
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*/
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typedef union {
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struct {
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/** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
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* core0 sp region configuration regsiter
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*/
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uint32_t core_0_sp_min:32;
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};
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uint32_t val;
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} assist_debug_core_0_sp_min_reg_t;
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/** Type of core_0_sp_max register
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* stack max value
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*/
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typedef union {
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struct {
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/** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
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* core0 sp pc status register
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*/
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uint32_t core_0_sp_max:32;
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};
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uint32_t val;
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} assist_debug_core_0_sp_max_reg_t;
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/** Type of core_0_sp_pc register
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* stack monitor pc status register
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*/
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typedef union {
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struct {
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/** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
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* This regsiter stores the PC when trigger stack monitor.
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*/
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uint32_t core_0_sp_pc:32;
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};
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uint32_t val;
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} assist_debug_core_0_sp_pc_reg_t;
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/** Type of core_1_intr_ena register
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* core1 monitor enable configuration register
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*/
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typedef union {
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struct {
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/** core_1_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
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* Core1 dram0 area0 read monitor enable
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*/
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uint32_t core_1_area_dram0_0_rd_ena:1;
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/** core_1_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
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* Core1 dram0 area0 write monitor enable
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*/
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uint32_t core_1_area_dram0_0_wr_ena:1;
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/** core_1_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
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* Core1 dram0 area1 read monitor enable
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*/
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uint32_t core_1_area_dram0_1_rd_ena:1;
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/** core_1_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
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* Core1 dram0 area1 write monitor enable
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*/
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uint32_t core_1_area_dram0_1_wr_ena:1;
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/** core_1_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
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* Core1 PIF area0 read monitor enable
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*/
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uint32_t core_1_area_pif_0_rd_ena:1;
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/** core_1_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
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* Core1 PIF area0 write monitor enable
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*/
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uint32_t core_1_area_pif_0_wr_ena:1;
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/** core_1_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
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* Core1 PIF area1 read monitor enable
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*/
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uint32_t core_1_area_pif_1_rd_ena:1;
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/** core_1_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
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* Core1 PIF area1 write monitor enable
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*/
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uint32_t core_1_area_pif_1_wr_ena:1;
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/** core_1_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
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* Core1 stackpoint underflow monitor enable
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*/
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uint32_t core_1_sp_spill_min_ena:1;
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/** core_1_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
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* Core1 stackpoint overflow monitor enable
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*/
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uint32_t core_1_sp_spill_max_ena:1;
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uint32_t reserved_10:22;
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};
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uint32_t val;
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} assist_debug_core_1_intr_ena_reg_t;
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/** Type of core_1_area_dram0_0_min register
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* core1 dram0 region0 addr configuration register
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*/
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typedef union {
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struct {
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/** core_1_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
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* Core1 dram0 region0 start addr
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*/
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uint32_t core_1_area_dram0_0_min:32;
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};
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uint32_t val;
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} assist_debug_core_1_area_dram0_0_min_reg_t;
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/** Type of core_1_area_dram0_0_max register
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* core1 dram0 region0 addr configuration register
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*/
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typedef union {
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struct {
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/** core_1_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
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* Core1 dram0 region0 end addr
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*/
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uint32_t core_1_area_dram0_0_max:32;
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};
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uint32_t val;
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} assist_debug_core_1_area_dram0_0_max_reg_t;
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/** Type of core_1_area_dram0_1_min register
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* core1 dram0 region1 addr configuration register
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*/
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typedef union {
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struct {
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/** core_1_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
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* Core1 dram0 region1 start addr
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*/
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uint32_t core_1_area_dram0_1_min:32;
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};
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uint32_t val;
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} assist_debug_core_1_area_dram0_1_min_reg_t;
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/** Type of core_1_area_dram0_1_max register
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* core1 dram0 region1 addr configuration register
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*/
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typedef union {
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struct {
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/** core_1_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
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* Core1 dram0 region1 end addr
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*/
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uint32_t core_1_area_dram0_1_max:32;
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};
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uint32_t val;
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} assist_debug_core_1_area_dram0_1_max_reg_t;
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/** Type of core_1_area_pif_0_min register
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* core1 PIF region0 addr configuration register
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*/
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typedef union {
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struct {
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/** core_1_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
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* Core1 PIF region0 start addr
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*/
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uint32_t core_1_area_pif_0_min:32;
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};
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uint32_t val;
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} assist_debug_core_1_area_pif_0_min_reg_t;
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/** Type of core_1_area_pif_0_max register
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* core1 PIF region0 addr configuration register
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*/
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typedef union {
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struct {
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/** core_1_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
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* Core1 PIF region0 end addr
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*/
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uint32_t core_1_area_pif_0_max:32;
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};
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uint32_t val;
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} assist_debug_core_1_area_pif_0_max_reg_t;
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/** Type of core_1_area_pif_1_min register
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* core1 PIF region1 addr configuration register
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*/
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typedef union {
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struct {
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/** core_1_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
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* Core1 PIF region1 start addr
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*/
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uint32_t core_1_area_pif_1_min:32;
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};
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uint32_t val;
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} assist_debug_core_1_area_pif_1_min_reg_t;
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/** Type of core_1_area_pif_1_max register
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* core1 PIF region1 addr configuration register
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*/
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typedef union {
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struct {
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/** core_1_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
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* Core1 PIF region1 end addr
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*/
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uint32_t core_1_area_pif_1_max:32;
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};
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uint32_t val;
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} assist_debug_core_1_area_pif_1_max_reg_t;
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/** Type of core_1_area_pc register
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* core1 area pc status register
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*/
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typedef union {
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struct {
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/** core_1_area_pc : RO; bitpos: [31:0]; default: 0;
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* the stackpointer when first touch region monitor interrupt
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*/
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uint32_t core_1_area_pc:32;
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};
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uint32_t val;
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} assist_debug_core_1_area_pc_reg_t;
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/** Type of core_1_area_sp register
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* core1 area sp status register
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*/
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typedef union {
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struct {
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/** core_1_area_sp : RO; bitpos: [31:0]; default: 0;
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* the PC when first touch region monitor interrupt
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*/
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uint32_t core_1_area_sp:32;
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};
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uint32_t val;
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} assist_debug_core_1_area_sp_reg_t;
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/** Type of core_1_sp_min register
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* stack min value
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*/
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typedef union {
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struct {
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/** core_1_sp_min : R/W; bitpos: [31:0]; default: 0;
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* core1 sp region configuration regsiter
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*/
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uint32_t core_1_sp_min:32;
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};
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uint32_t val;
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} assist_debug_core_1_sp_min_reg_t;
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/** Type of core_1_sp_max register
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* stack max value
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*/
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typedef union {
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struct {
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/** core_1_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
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* core1 sp pc status register
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*/
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uint32_t core_1_sp_max:32;
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};
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uint32_t val;
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} assist_debug_core_1_sp_max_reg_t;
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/** Type of core_1_sp_pc register
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* stack monitor pc status register
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*/
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typedef union {
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struct {
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/** core_1_sp_pc : RO; bitpos: [31:0]; default: 0;
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* This regsiter stores the PC when trigger stack monitor.
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*/
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uint32_t core_1_sp_pc:32;
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};
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uint32_t val;
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} assist_debug_core_1_sp_pc_reg_t;
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/** Group: interrupt configuration register */
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/** Type of core_0_intr_raw register
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* core0 monitor interrupt status register
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*/
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typedef union {
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struct {
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/** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
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* Core0 dram0 area0 read monitor interrupt status
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*/
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uint32_t core_0_area_dram0_0_rd_raw:1;
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/** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
|
|
* Core0 dram0 area0 write monitor interrupt status
|
|
*/
|
|
uint32_t core_0_area_dram0_0_wr_raw:1;
|
|
/** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
|
|
* Core0 dram0 area1 read monitor interrupt status
|
|
*/
|
|
uint32_t core_0_area_dram0_1_rd_raw:1;
|
|
/** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
|
|
* Core0 dram0 area1 write monitor interrupt status
|
|
*/
|
|
uint32_t core_0_area_dram0_1_wr_raw:1;
|
|
/** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
|
|
* Core0 PIF area0 read monitor interrupt status
|
|
*/
|
|
uint32_t core_0_area_pif_0_rd_raw:1;
|
|
/** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
|
|
* Core0 PIF area0 write monitor interrupt status
|
|
*/
|
|
uint32_t core_0_area_pif_0_wr_raw:1;
|
|
/** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
|
|
* Core0 PIF area1 read monitor interrupt status
|
|
*/
|
|
uint32_t core_0_area_pif_1_rd_raw:1;
|
|
/** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
|
|
* Core0 PIF area1 write monitor interrupt status
|
|
*/
|
|
uint32_t core_0_area_pif_1_wr_raw:1;
|
|
/** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
|
|
* Core0 stackpoint underflow monitor interrupt status
|
|
*/
|
|
uint32_t core_0_sp_spill_min_raw:1;
|
|
/** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
|
|
* Core0 stackpoint overflow monitor interrupt status
|
|
*/
|
|
uint32_t core_0_sp_spill_max_raw:1;
|
|
uint32_t reserved_10:22;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_intr_raw_reg_t;
|
|
|
|
/** Type of core_0_intr_rls register
|
|
* core0 monitor interrupt enable register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
|
|
* Core0 dram0 area0 read monitor interrupt enable
|
|
*/
|
|
uint32_t core_0_area_dram0_0_rd_rls:1;
|
|
/** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
|
|
* Core0 dram0 area0 write monitor interrupt enable
|
|
*/
|
|
uint32_t core_0_area_dram0_0_wr_rls:1;
|
|
/** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
|
|
* Core0 dram0 area1 read monitor interrupt enable
|
|
*/
|
|
uint32_t core_0_area_dram0_1_rd_rls:1;
|
|
/** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
|
|
* Core0 dram0 area1 write monitor interrupt enable
|
|
*/
|
|
uint32_t core_0_area_dram0_1_wr_rls:1;
|
|
/** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
|
|
* Core0 PIF area0 read monitor interrupt enable
|
|
*/
|
|
uint32_t core_0_area_pif_0_rd_rls:1;
|
|
/** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
|
|
* Core0 PIF area0 write monitor interrupt enable
|
|
*/
|
|
uint32_t core_0_area_pif_0_wr_rls:1;
|
|
/** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
|
|
* Core0 PIF area1 read monitor interrupt enable
|
|
*/
|
|
uint32_t core_0_area_pif_1_rd_rls:1;
|
|
/** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
|
|
* Core0 PIF area1 write monitor interrupt enable
|
|
*/
|
|
uint32_t core_0_area_pif_1_wr_rls:1;
|
|
/** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
|
|
* Core0 stackpoint underflow monitor interrupt enable
|
|
*/
|
|
uint32_t core_0_sp_spill_min_rls:1;
|
|
/** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
|
|
* Core0 stackpoint overflow monitor interrupt enable
|
|
*/
|
|
uint32_t core_0_sp_spill_max_rls:1;
|
|
uint32_t reserved_10:22;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_intr_rls_reg_t;
|
|
|
|
/** Type of core_0_intr_clr register
|
|
* core0 monitor interrupt clr register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
|
|
* Core0 dram0 area0 read monitor interrupt clr
|
|
*/
|
|
uint32_t core_0_area_dram0_0_rd_clr:1;
|
|
/** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
|
|
* Core0 dram0 area0 write monitor interrupt clr
|
|
*/
|
|
uint32_t core_0_area_dram0_0_wr_clr:1;
|
|
/** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
|
|
* Core0 dram0 area1 read monitor interrupt clr
|
|
*/
|
|
uint32_t core_0_area_dram0_1_rd_clr:1;
|
|
/** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
|
|
* Core0 dram0 area1 write monitor interrupt clr
|
|
*/
|
|
uint32_t core_0_area_dram0_1_wr_clr:1;
|
|
/** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
|
|
* Core0 PIF area0 read monitor interrupt clr
|
|
*/
|
|
uint32_t core_0_area_pif_0_rd_clr:1;
|
|
/** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
|
|
* Core0 PIF area0 write monitor interrupt clr
|
|
*/
|
|
uint32_t core_0_area_pif_0_wr_clr:1;
|
|
/** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
|
|
* Core0 PIF area1 read monitor interrupt clr
|
|
*/
|
|
uint32_t core_0_area_pif_1_rd_clr:1;
|
|
/** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
|
|
* Core0 PIF area1 write monitor interrupt clr
|
|
*/
|
|
uint32_t core_0_area_pif_1_wr_clr:1;
|
|
/** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
|
|
* Core0 stackpoint underflow monitor interrupt clr
|
|
*/
|
|
uint32_t core_0_sp_spill_min_clr:1;
|
|
/** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
|
|
* Core0 stackpoint overflow monitor interrupt clr
|
|
*/
|
|
uint32_t core_0_sp_spill_max_clr:1;
|
|
uint32_t reserved_10:22;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_intr_clr_reg_t;
|
|
|
|
/** Type of core_1_intr_raw register
|
|
* core1 monitor interrupt status register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
|
|
* Core1 dram0 area0 read monitor interrupt status
|
|
*/
|
|
uint32_t core_1_area_dram0_0_rd_raw:1;
|
|
/** core_1_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
|
|
* Core1 dram0 area0 write monitor interrupt status
|
|
*/
|
|
uint32_t core_1_area_dram0_0_wr_raw:1;
|
|
/** core_1_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
|
|
* Core1 dram0 area1 read monitor interrupt status
|
|
*/
|
|
uint32_t core_1_area_dram0_1_rd_raw:1;
|
|
/** core_1_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
|
|
* Core1 dram0 area1 write monitor interrupt status
|
|
*/
|
|
uint32_t core_1_area_dram0_1_wr_raw:1;
|
|
/** core_1_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
|
|
* Core1 PIF area0 read monitor interrupt status
|
|
*/
|
|
uint32_t core_1_area_pif_0_rd_raw:1;
|
|
/** core_1_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
|
|
* Core1 PIF area0 write monitor interrupt status
|
|
*/
|
|
uint32_t core_1_area_pif_0_wr_raw:1;
|
|
/** core_1_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
|
|
* Core1 PIF area1 read monitor interrupt status
|
|
*/
|
|
uint32_t core_1_area_pif_1_rd_raw:1;
|
|
/** core_1_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
|
|
* Core1 PIF area1 write monitor interrupt status
|
|
*/
|
|
uint32_t core_1_area_pif_1_wr_raw:1;
|
|
/** core_1_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
|
|
* Core1 stackpoint underflow monitor interrupt status
|
|
*/
|
|
uint32_t core_1_sp_spill_min_raw:1;
|
|
/** core_1_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
|
|
* Core1 stackpoint overflow monitor interrupt status
|
|
*/
|
|
uint32_t core_1_sp_spill_max_raw:1;
|
|
uint32_t reserved_10:22;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_intr_raw_reg_t;
|
|
|
|
/** Type of core_1_intr_rls register
|
|
* core1 monitor interrupt enable register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
|
|
* Core1 dram0 area0 read monitor interrupt enable
|
|
*/
|
|
uint32_t core_1_area_dram0_0_rd_rls:1;
|
|
/** core_1_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
|
|
* Core1 dram0 area0 write monitor interrupt enable
|
|
*/
|
|
uint32_t core_1_area_dram0_0_wr_rls:1;
|
|
/** core_1_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
|
|
* Core1 dram0 area1 read monitor interrupt enable
|
|
*/
|
|
uint32_t core_1_area_dram0_1_rd_rls:1;
|
|
/** core_1_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
|
|
* Core1 dram0 area1 write monitor interrupt enable
|
|
*/
|
|
uint32_t core_1_area_dram0_1_wr_rls:1;
|
|
/** core_1_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
|
|
* Core1 PIF area0 read monitor interrupt enable
|
|
*/
|
|
uint32_t core_1_area_pif_0_rd_rls:1;
|
|
/** core_1_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
|
|
* Core1 PIF area0 write monitor interrupt enable
|
|
*/
|
|
uint32_t core_1_area_pif_0_wr_rls:1;
|
|
/** core_1_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
|
|
* Core1 PIF area1 read monitor interrupt enable
|
|
*/
|
|
uint32_t core_1_area_pif_1_rd_rls:1;
|
|
/** core_1_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
|
|
* Core1 PIF area1 write monitor interrupt enable
|
|
*/
|
|
uint32_t core_1_area_pif_1_wr_rls:1;
|
|
/** core_1_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
|
|
* Core1 stackpoint underflow monitor interrupt enable
|
|
*/
|
|
uint32_t core_1_sp_spill_min_rls:1;
|
|
/** core_1_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
|
|
* Core1 stackpoint overflow monitor interrupt enable
|
|
*/
|
|
uint32_t core_1_sp_spill_max_rls:1;
|
|
uint32_t reserved_10:22;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_intr_rls_reg_t;
|
|
|
|
/** Type of core_1_intr_clr register
|
|
* core1 monitor interrupt clr register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
|
|
* Core1 dram0 area0 read monitor interrupt clr
|
|
*/
|
|
uint32_t core_1_area_dram0_0_rd_clr:1;
|
|
/** core_1_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
|
|
* Core1 dram0 area0 write monitor interrupt clr
|
|
*/
|
|
uint32_t core_1_area_dram0_0_wr_clr:1;
|
|
/** core_1_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
|
|
* Core1 dram0 area1 read monitor interrupt clr
|
|
*/
|
|
uint32_t core_1_area_dram0_1_rd_clr:1;
|
|
/** core_1_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
|
|
* Core1 dram0 area1 write monitor interrupt clr
|
|
*/
|
|
uint32_t core_1_area_dram0_1_wr_clr:1;
|
|
/** core_1_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
|
|
* Core1 PIF area0 read monitor interrupt clr
|
|
*/
|
|
uint32_t core_1_area_pif_0_rd_clr:1;
|
|
/** core_1_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
|
|
* Core1 PIF area0 write monitor interrupt clr
|
|
*/
|
|
uint32_t core_1_area_pif_0_wr_clr:1;
|
|
/** core_1_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
|
|
* Core1 PIF area1 read monitor interrupt clr
|
|
*/
|
|
uint32_t core_1_area_pif_1_rd_clr:1;
|
|
/** core_1_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
|
|
* Core1 PIF area1 write monitor interrupt clr
|
|
*/
|
|
uint32_t core_1_area_pif_1_wr_clr:1;
|
|
/** core_1_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
|
|
* Core1 stackpoint underflow monitor interrupt clr
|
|
*/
|
|
uint32_t core_1_sp_spill_min_clr:1;
|
|
/** core_1_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
|
|
* Core1 stackpoint overflow monitor interrupt clr
|
|
*/
|
|
uint32_t core_1_sp_spill_max_clr:1;
|
|
uint32_t reserved_10:22;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_intr_clr_reg_t;
|
|
|
|
|
|
/** Group: pc reording configuration register */
|
|
/** Type of core_0_rcd_en register
|
|
* record enable configuration register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
|
|
* Set 1 to enable record PC
|
|
*/
|
|
uint32_t core_0_rcd_recorden:1;
|
|
/** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
|
|
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
|
|
*/
|
|
uint32_t core_0_rcd_pdebugen:1;
|
|
uint32_t reserved_2:30;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_rcd_en_reg_t;
|
|
|
|
/** Type of core_1_rcd_en register
|
|
* record enable configuration register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_rcd_recorden : R/W; bitpos: [0]; default: 0;
|
|
* Set 1 to enable record PC
|
|
*/
|
|
uint32_t core_1_rcd_recorden:1;
|
|
/** core_1_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
|
|
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
|
|
*/
|
|
uint32_t core_1_rcd_pdebugen:1;
|
|
uint32_t reserved_2:30;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_rcd_en_reg_t;
|
|
|
|
|
|
/** Group: pc reording status register */
|
|
/** Type of core_0_rcd_pdebugpc register
|
|
* record status regsiter
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
|
|
* recorded PC
|
|
*/
|
|
uint32_t core_0_rcd_pdebugpc:32;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_rcd_pdebugpc_reg_t;
|
|
|
|
/** Type of core_0_rcd_pdebugsp register
|
|
* record status regsiter
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
|
|
* recorded sp
|
|
*/
|
|
uint32_t core_0_rcd_pdebugsp:32;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_rcd_pdebugsp_reg_t;
|
|
|
|
/** Type of core_1_rcd_pdebugpc register
|
|
* record status regsiter
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
|
|
* recorded PC
|
|
*/
|
|
uint32_t core_1_rcd_pdebugpc:32;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_rcd_pdebugpc_reg_t;
|
|
|
|
/** Type of core_1_rcd_pdebugsp register
|
|
* record status regsiter
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
|
|
* recorded sp
|
|
*/
|
|
uint32_t core_1_rcd_pdebugsp:32;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_rcd_pdebugsp_reg_t;
|
|
|
|
|
|
/** Group: exception monitor regsiter */
|
|
/** Type of core_0_iram0_exception_monitor_0 register
|
|
* exception monitor status register0
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
|
|
* reg_core_0_iram0_recording_addr_0
|
|
*/
|
|
uint32_t core_0_iram0_recording_addr_0:24;
|
|
/** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
|
|
* reg_core_0_iram0_recording_wr_0
|
|
*/
|
|
uint32_t core_0_iram0_recording_wr_0:1;
|
|
/** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
|
|
* reg_core_0_iram0_recording_loadstore_0
|
|
*/
|
|
uint32_t core_0_iram0_recording_loadstore_0:1;
|
|
uint32_t reserved_26:6;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
|
|
|
|
/** Type of core_0_iram0_exception_monitor_1 register
|
|
* exception monitor status register1
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
|
|
* reg_core_0_iram0_recording_addr_1
|
|
*/
|
|
uint32_t core_0_iram0_recording_addr_1:24;
|
|
/** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
|
|
* reg_core_0_iram0_recording_wr_1
|
|
*/
|
|
uint32_t core_0_iram0_recording_wr_1:1;
|
|
/** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
|
|
* reg_core_0_iram0_recording_loadstore_1
|
|
*/
|
|
uint32_t core_0_iram0_recording_loadstore_1:1;
|
|
uint32_t reserved_26:6;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
|
|
|
|
/** Type of core_0_dram0_exception_monitor_0 register
|
|
* exception monitor status register2
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
|
|
* reg_core_0_dram0_recording_wr_0
|
|
*/
|
|
uint32_t core_0_dram0_recording_wr_0:1;
|
|
/** core_0_dram0_recording_byteen_0 : RO; bitpos: [16:1]; default: 0;
|
|
* reg_core_0_dram0_recording_byteen_0
|
|
*/
|
|
uint32_t core_0_dram0_recording_byteen_0:16;
|
|
uint32_t reserved_17:15;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
|
|
|
|
/** Type of core_0_dram0_exception_monitor_1 register
|
|
* exception monitor status register3
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
|
|
* reg_core_0_dram0_recording_addr_0
|
|
*/
|
|
uint32_t core_0_dram0_recording_addr_0:24;
|
|
uint32_t reserved_24:8;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
|
|
|
|
/** Type of core_0_dram0_exception_monitor_2 register
|
|
* exception monitor status register4
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
|
|
* reg_core_0_dram0_recording_pc_0
|
|
*/
|
|
uint32_t core_0_dram0_recording_pc_0:32;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
|
|
|
|
/** Type of core_0_dram0_exception_monitor_3 register
|
|
* exception monitor status register5
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
|
|
* reg_core_0_dram0_recording_wr_1
|
|
*/
|
|
uint32_t core_0_dram0_recording_wr_1:1;
|
|
/** core_0_dram0_recording_byteen_1 : RO; bitpos: [16:1]; default: 0;
|
|
* reg_core_0_dram0_recording_byteen_1
|
|
*/
|
|
uint32_t core_0_dram0_recording_byteen_1:16;
|
|
uint32_t reserved_17:15;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
|
|
|
|
/** Type of core_0_dram0_exception_monitor_4 register
|
|
* exception monitor status register6
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
|
|
* reg_core_0_dram0_recording_addr_1
|
|
*/
|
|
uint32_t core_0_dram0_recording_addr_1:24;
|
|
uint32_t reserved_24:8;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_dram0_exception_monitor_4_reg_t;
|
|
|
|
/** Type of core_0_dram0_exception_monitor_5 register
|
|
* exception monitor status register7
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
|
|
* reg_core_0_dram0_recording_pc_1
|
|
*/
|
|
uint32_t core_0_dram0_recording_pc_1:32;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_dram0_exception_monitor_5_reg_t;
|
|
|
|
/** Type of core_1_iram0_exception_monitor_0 register
|
|
* exception monitor status register0
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
|
|
* reg_core_1_iram0_recording_addr_0
|
|
*/
|
|
uint32_t core_1_iram0_recording_addr_0:24;
|
|
/** core_1_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
|
|
* reg_core_1_iram0_recording_wr_0
|
|
*/
|
|
uint32_t core_1_iram0_recording_wr_0:1;
|
|
/** core_1_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
|
|
* reg_core_1_iram0_recording_loadstore_0
|
|
*/
|
|
uint32_t core_1_iram0_recording_loadstore_0:1;
|
|
uint32_t reserved_26:6;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_iram0_exception_monitor_0_reg_t;
|
|
|
|
/** Type of core_1_iram0_exception_monitor_1 register
|
|
* exception monitor status register1
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
|
|
* reg_core_1_iram0_recording_addr_1
|
|
*/
|
|
uint32_t core_1_iram0_recording_addr_1:24;
|
|
/** core_1_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
|
|
* reg_core_1_iram0_recording_wr_1
|
|
*/
|
|
uint32_t core_1_iram0_recording_wr_1:1;
|
|
/** core_1_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
|
|
* reg_core_1_iram0_recording_loadstore_1
|
|
*/
|
|
uint32_t core_1_iram0_recording_loadstore_1:1;
|
|
uint32_t reserved_26:6;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_iram0_exception_monitor_1_reg_t;
|
|
|
|
/** Type of core_1_dram0_exception_monitor_0 register
|
|
* exception monitor status register2
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
|
|
* reg_core_1_dram0_recording_wr_0
|
|
*/
|
|
uint32_t core_1_dram0_recording_wr_0:1;
|
|
/** core_1_dram0_recording_byteen_0 : RO; bitpos: [16:1]; default: 0;
|
|
* reg_core_1_dram0_recording_byteen_0
|
|
*/
|
|
uint32_t core_1_dram0_recording_byteen_0:16;
|
|
uint32_t reserved_17:15;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_dram0_exception_monitor_0_reg_t;
|
|
|
|
/** Type of core_1_dram0_exception_monitor_1 register
|
|
* exception monitor status register3
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
|
|
* reg_core_1_dram0_recording_addr_0
|
|
*/
|
|
uint32_t core_1_dram0_recording_addr_0:24;
|
|
uint32_t reserved_24:8;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_dram0_exception_monitor_1_reg_t;
|
|
|
|
/** Type of core_1_dram0_exception_monitor_2 register
|
|
* exception monitor status register4
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
|
|
* reg_core_1_dram0_recording_pc_0
|
|
*/
|
|
uint32_t core_1_dram0_recording_pc_0:32;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_dram0_exception_monitor_2_reg_t;
|
|
|
|
/** Type of core_1_dram0_exception_monitor_3 register
|
|
* exception monitor status register5
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
|
|
* reg_core_1_dram0_recording_wr_1
|
|
*/
|
|
uint32_t core_1_dram0_recording_wr_1:1;
|
|
/** core_1_dram0_recording_byteen_1 : RO; bitpos: [16:1]; default: 0;
|
|
* reg_core_1_dram0_recording_byteen_1
|
|
*/
|
|
uint32_t core_1_dram0_recording_byteen_1:16;
|
|
uint32_t reserved_17:15;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_dram0_exception_monitor_3_reg_t;
|
|
|
|
/** Type of core_1_dram0_exception_monitor_4 register
|
|
* exception monitor status register6
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
|
|
* reg_core_1_dram0_recording_addr_1
|
|
*/
|
|
uint32_t core_1_dram0_recording_addr_1:24;
|
|
uint32_t reserved_24:8;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_dram0_exception_monitor_4_reg_t;
|
|
|
|
/** Type of core_1_dram0_exception_monitor_5 register
|
|
* exception monitor status register7
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
|
|
* reg_core_1_dram0_recording_pc_1
|
|
*/
|
|
uint32_t core_1_dram0_recording_pc_1:32;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_dram0_exception_monitor_5_reg_t;
|
|
|
|
/** Type of core_x_iram0_dram0_exception_monitor_0 register
|
|
* exception monitor status register6
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
|
|
* reg_core_x_iram0_dram0_limit_cycle_0
|
|
*/
|
|
uint32_t core_x_iram0_dram0_limit_cycle_0:20;
|
|
uint32_t reserved_20:12;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
|
|
|
|
/** Type of core_x_iram0_dram0_exception_monitor_1 register
|
|
* exception monitor status register7
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
|
|
* reg_core_x_iram0_dram0_limit_cycle_1
|
|
*/
|
|
uint32_t core_x_iram0_dram0_limit_cycle_1:20;
|
|
uint32_t reserved_20:12;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
|
|
|
|
|
|
/** Group: cpu status registers */
|
|
/** Type of core_0_lastpc_before_exception register
|
|
* cpu status register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
|
|
* cpu's lastpc before exception
|
|
*/
|
|
uint32_t core_0_lastpc_before_exc:32;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_lastpc_before_exception_reg_t;
|
|
|
|
/** Type of core_0_debug_mode register
|
|
* cpu status register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_0_debug_mode : RO; bitpos: [0]; default: 0;
|
|
* cpu debug mode status, 1 means cpu enter debug mode.
|
|
*/
|
|
uint32_t core_0_debug_mode:1;
|
|
/** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
|
|
* cpu debug_module active status
|
|
*/
|
|
uint32_t core_0_debug_module_active:1;
|
|
uint32_t reserved_2:30;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_0_debug_mode_reg_t;
|
|
|
|
/** Type of core_1_lastpc_before_exception register
|
|
* cpu status register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
|
|
* cpu's lastpc before exception
|
|
*/
|
|
uint32_t core_1_lastpc_before_exc:32;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_lastpc_before_exception_reg_t;
|
|
|
|
/** Type of core_1_debug_mode register
|
|
* cpu status register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** core_1_debug_mode : RO; bitpos: [0]; default: 0;
|
|
* cpu debug mode status, 1 means cpu enter debug mode.
|
|
*/
|
|
uint32_t core_1_debug_mode:1;
|
|
/** core_1_debug_module_active : RO; bitpos: [1]; default: 0;
|
|
* cpu debug_module active status
|
|
*/
|
|
uint32_t core_1_debug_module_active:1;
|
|
uint32_t reserved_2:30;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_core_1_debug_mode_reg_t;
|
|
|
|
|
|
/** Group: Configuration Registers */
|
|
/** Type of clock_gate register
|
|
* clock register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** clk_en : R/W; bitpos: [0]; default: 1;
|
|
* Set 1 force on the clock gate
|
|
*/
|
|
uint32_t clk_en:1;
|
|
uint32_t reserved_1:31;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_clock_gate_reg_t;
|
|
|
|
/** Type of date register
|
|
* version register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
|
|
* version register
|
|
*/
|
|
uint32_t assist_debug_date:28;
|
|
uint32_t reserved_28:4;
|
|
};
|
|
uint32_t val;
|
|
} assist_debug_date_reg_t;
|
|
|
|
|
|
typedef struct {
|
|
volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
|
|
volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
|
|
volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
|
|
volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
|
|
volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
|
|
volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
|
|
volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
|
|
volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
|
|
volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
|
|
volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
|
|
volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
|
|
volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
|
|
volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
|
|
volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
|
|
volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
|
|
volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
|
|
volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
|
|
volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
|
|
volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
|
|
volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
|
|
volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
|
|
volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
|
|
volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
|
|
volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
|
|
volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
|
|
volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
|
|
volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4;
|
|
volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5;
|
|
volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
|
|
volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
|
|
uint32_t reserved_078[2];
|
|
volatile assist_debug_core_1_intr_ena_reg_t core_1_intr_ena;
|
|
volatile assist_debug_core_1_intr_raw_reg_t core_1_intr_raw;
|
|
volatile assist_debug_core_1_intr_rls_reg_t core_1_intr_rls;
|
|
volatile assist_debug_core_1_intr_clr_reg_t core_1_intr_clr;
|
|
volatile assist_debug_core_1_area_dram0_0_min_reg_t core_1_area_dram0_0_min;
|
|
volatile assist_debug_core_1_area_dram0_0_max_reg_t core_1_area_dram0_0_max;
|
|
volatile assist_debug_core_1_area_dram0_1_min_reg_t core_1_area_dram0_1_min;
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volatile assist_debug_core_1_area_dram0_1_max_reg_t core_1_area_dram0_1_max;
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volatile assist_debug_core_1_area_pif_0_min_reg_t core_1_area_pif_0_min;
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volatile assist_debug_core_1_area_pif_0_max_reg_t core_1_area_pif_0_max;
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volatile assist_debug_core_1_area_pif_1_min_reg_t core_1_area_pif_1_min;
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volatile assist_debug_core_1_area_pif_1_max_reg_t core_1_area_pif_1_max;
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volatile assist_debug_core_1_area_pc_reg_t core_1_area_pc;
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volatile assist_debug_core_1_area_sp_reg_t core_1_area_sp;
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volatile assist_debug_core_1_sp_min_reg_t core_1_sp_min;
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volatile assist_debug_core_1_sp_max_reg_t core_1_sp_max;
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volatile assist_debug_core_1_sp_pc_reg_t core_1_sp_pc;
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volatile assist_debug_core_1_rcd_en_reg_t core_1_rcd_en;
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volatile assist_debug_core_1_rcd_pdebugpc_reg_t core_1_rcd_pdebugpc;
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volatile assist_debug_core_1_rcd_pdebugsp_reg_t core_1_rcd_pdebugsp;
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volatile assist_debug_core_1_iram0_exception_monitor_0_reg_t core_1_iram0_exception_monitor_0;
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volatile assist_debug_core_1_iram0_exception_monitor_1_reg_t core_1_iram0_exception_monitor_1;
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volatile assist_debug_core_1_dram0_exception_monitor_0_reg_t core_1_dram0_exception_monitor_0;
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volatile assist_debug_core_1_dram0_exception_monitor_1_reg_t core_1_dram0_exception_monitor_1;
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volatile assist_debug_core_1_dram0_exception_monitor_2_reg_t core_1_dram0_exception_monitor_2;
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volatile assist_debug_core_1_dram0_exception_monitor_3_reg_t core_1_dram0_exception_monitor_3;
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volatile assist_debug_core_1_dram0_exception_monitor_4_reg_t core_1_dram0_exception_monitor_4;
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volatile assist_debug_core_1_dram0_exception_monitor_5_reg_t core_1_dram0_exception_monitor_5;
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volatile assist_debug_core_1_lastpc_before_exception_reg_t core_1_lastpc_before_exception;
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volatile assist_debug_core_1_debug_mode_reg_t core_1_debug_mode;
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uint32_t reserved_0f8[2];
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volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
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volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
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volatile assist_debug_clock_gate_reg_t clock_gate;
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uint32_t reserved_10c[188];
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volatile assist_debug_date_reg_t date;
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} assist_debug_dev_t;
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#ifndef __cplusplus
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_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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