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esp-idf/components/esp_system/port/soc
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Gustavo Henrique Nihei 3cbac3dd1d esp_system: Ensure TIMG0 clock is always enabled during normal operation 
If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
registers (Flashboot protection included) will be re-enabled, and some
seconds later, will trigger an unintended reset.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-06 04:58:11 +00:00
..
esp32 esp_system: Ensure TIMG0 clock is always enabled during normal operation 2023-03-06 04:58:11 +00:00
esp32c2 esp_system: Ensure TIMG0 clock is always enabled during normal operation 2023-03-06 04:58:11 +00:00
esp32c3 esp_system: Ensure TIMG0 clock is always enabled during normal operation 2023-03-06 04:58:11 +00:00
esp32c6 esp_system: Ensure TIMG0 clock is always enabled during normal operation 2023-03-06 04:58:11 +00:00
esp32h2 esp_system: Ensure TIMG0 clock is always enabled during normal operation 2023-03-06 04:58:11 +00:00
esp32h4 esp_system: Ensure TIMG0 clock is always enabled during normal operation 2023-03-06 04:58:11 +00:00
esp32s2 esp_system: Ensure TIMG0 clock is always enabled during normal operation 2023-03-06 04:58:11 +00:00
esp32s3 esp_system: Ensure TIMG0 clock is always enabled during normal operation 2023-03-06 04:58:11 +00:00
linux feat(esp_system): Partially buildable on Linux now 2022-11-16 09:03:09 +01:00