esp-idf/components/ulp/ld/esp32s2.ulp.riscv.ld
Angus Gratton 3ee4370578 esp32s2 riscv ulp: Ensure reset vector is always at offset 0x0
Previous linker script relied on nothing else using the .text section

As reported at https://esp32.com/viewtopic.php?f=2&t=20734&p=75997
2021-05-06 09:25:32 +10:00

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658 B
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#include "sdkconfig.h"
ENTRY(reset_vector)
MEMORY
{
ram(RW) : ORIGIN = 0, LENGTH = CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
}
SECTIONS
{
. = ORIGIN(ram);
.text :
{
*start.S.obj(.text.vectors) /* Default reset vector must link to offset 0x0 */
*(.text)
*(.text*)
} >ram
.rodata ALIGN(4):
{
*(.rodata)
*(.rodata*)
} > ram
.data ALIGN(4):
{
*(.data)
*(.data*)
*(.sdata)
*(.sdata*)
} > ram
.bss ALIGN(4) :
{
*(.bss)
*(.bss*)
*(.sbss)
*(.sbss*)
} >ram
__stack_top = ORIGIN(ram) + LENGTH(ram);
}