Mahavir Jain f790fe0e1f clk_gate_ll: fix issue with DS peripheral clk reset ... In ESP32-H2, every peripheral reset enable bit is in different register (unlike some of the previous SoCs) and hence they must be handled with multiple register write operations. This allows AES, MPI peripherals to works correctly after DS peripheral has done some operations.		2023-02-09 17:11:37 +05:30
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include/hal	clk_gate_ll: fix issue with DS peripheral clk reset	2023-02-09 17:11:37 +05:30
clk_tree_hal.c	clk_tree: Add a general API to get the frequency of different clocks	2023-01-17 11:30:24 +08:00
efuse_hal.c	ESP32-H2: Last MR for g0 component support, (only hal left)	2022-12-05 17:32:21 +08:00