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clk_gate_ll: fix issue with DS peripheral clk reset
In ESP32-H2, every peripheral reset enable bit is in different register (unlike some of the previous SoCs) and hence they must be handled with multiple register write operations. This allows AES, MPI peripherals to works correctly after DS peripheral has done some operations.
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@ -129,29 +129,24 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
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case PERIPH_ETM_MODULE:
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return PCR_ETM_RST_EN;
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case PERIPH_AES_MODULE:
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if (enable == true) {
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// Clear reset on digital signature, otherwise AES unit is held in reset also.
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return (PCR_AES_RST_EN | PCR_DS_RST_EN);
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} else {
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//Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
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return PCR_AES_RST_EN;
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}
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if (enable == true) {
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// Clear reset on digital signature, otherwise AES unit is held in reset
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DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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}
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return PCR_AES_RST_EN;
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case PERIPH_SHA_MODULE:
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if (enable == true) {
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// Clear reset on digital signature and HMAC, otherwise SHA is held in reset
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return (PCR_SHA_RST_EN | PCR_DS_RST_EN | PCR_HMAC_RST_EN);
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} else {
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// Don't assert reset on secure boot, otherwise AES is held in reset
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return PCR_SHA_RST_EN;
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}
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if (enable == true) {
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// Clear reset on digital signature and HMAC, otherwise SHA is held in reset
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DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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DPORT_CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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}
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return PCR_SHA_RST_EN;
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case PERIPH_RSA_MODULE:
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if (enable == true) {
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/* also clear reset on digital signature, otherwise RSA is held in reset */
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return (PCR_RSA_RST_EN | PCR_DS_RST_EN);
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} else {
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/* don't reset digital signature unit, as this resets AES also */
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return PCR_RSA_RST_EN;
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}
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if (enable == true) {
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// Clear reset on digital signature, otherwise RSA is held in reset
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DPORT_CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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}
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return PCR_RSA_RST_EN;
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case PERIPH_HMAC_MODULE:
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return PCR_HMAC_RST_EN;
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case PERIPH_DS_MODULE:
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