esp-idf/components/riscv/include/riscv
Sudeep Mohanty d4ca7c246e fix(freertos): Fixed incorrect int level restoration on esp32p4
This commit fixes a bug where in the portENABLE_INTERRUPTS() macro
incorrectly restored the interrupt level to 1 (non-CLIC controller).
2024-01-05 11:00:56 +01:00
..
csr.h fix(riscv): supports 1 byte and larger than 64byte range watchpoint setting 2023-11-16 18:11:57 +08:00
encoding.h riscv: Add new arch-level component 2020-11-12 09:33:18 +11:00
instruction_decode.h interrupt: filter out reserved int number by decoding risc-v JAL instruction 2021-01-05 15:39:46 +08:00
interrupt.h fix(esp32p4): Fixed interrupt handling to use the CLIC controller 2023-08-31 12:16:08 +08:00
rv_utils.h fix(freertos): Fixed incorrect int level restoration on esp32p4 2024-01-05 11:00:56 +01:00
rvruntime-frames.h feat(riscv): implement coprocessors save area and FPU support 2023-10-23 11:10:28 +08:00
rvsleep-frames.h bugfix: fix pmp retention and add pma retention 2023-05-29 16:35:03 +08:00
semihosting.h semihosting: version 2 2022-05-05 09:12:42 +00:00