Sudeep Mohanty 96b152a01f ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2 ... This commit fixes an issue where in the ULP RISC-V I2C example causes a spurious wakeup of the main CPU because of a Trap signal when the ULP core does not meet the wakeup threshold values. This was due to the fact that the RTC_CNTL_COCPU_DONE signal was being set before the RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V core to not reset properly on each cycle. Closes https://github.com/espressif/esp-idf/issues/10301		2023-01-02 14:24:16 +01:00
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include/ulp_riscv	ulp-riscv: add support for using ADC as well as an example show-casing it.	2022-08-09 09:21:15 +08:00
start.S	esp32s2 riscv ulp: Ensure reset vector is always at offset 0x0	2021-05-06 09:25:32 +10:00
ulp_riscv_adc.c	ulp-riscv: add support for using ADC as well as an example show-casing it.	2022-08-09 09:21:15 +08:00
ulp_riscv_utils.c	ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2	2023-01-02 14:24:16 +01:00