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https://github.com/espressif/esp-idf.git
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1f6d7fa334
This commit adds a workaround for the TWAI listen only mode errata which is present on the ESP32, ESP32-S2, ESP32-S3, and ESP32-C3. twai_get_status_info() has also been updated to account for the fact that TEC/REC are frozen in listen only mode. Errata Description: When the TWAI controller is put into listen only mode, it should not influence the TWAI bus in any way (i.e., should never send a dominant bit). However, on the targets listed above, the TWAI controller will send dominant bits in an error frame (i.e., active error frame), even if the controller is set to listen only mode. Workaround: We can force the TWAI controller into the error passive state on startup (by setting the REC to >= 128). Since the TEC/REC are frozen in listen only mode, the TWAI controller will remain error passive and only send recessive bits (i.e., passive error frames), thus will not influence the TWAI bus. Closes https://github.com/espressif/esp-idf/issues/9157
207 lines
9.9 KiB
Plaintext
207 lines
9.9 KiB
Plaintext
menu "Driver configurations"
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menu "ADC configuration"
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config ADC_FORCE_XPD_FSM
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bool "Use the FSM to control ADC power"
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default n
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help
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ADC power can be controlled by the FSM instead of software. This allows the ADC to
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be shut off when it is not working leading to lower power consumption. However
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using the FSM control ADC power will increase the noise of ADC.
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config ADC_DISABLE_DAC
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bool "Disable DAC when ADC2 is used on GPIO 25 and 26"
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default y
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help
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If this is set, the ADC2 driver will disable the output of the DAC corresponding to the specified
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channel. This is the default value.
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For testing, disable this option so that we can measure the output of DAC by internal ADC.
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config ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3
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depends on IDF_TARGET_ESP32C3
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bool "Force use ADC2 continumous mode on ESP32C3"
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default n
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help
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On ESP32C3, ADC2 Digital Controller is not stable. Therefore,
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ADC2 continuous mode is not suggested on ESP32C3
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If you stick to this, you can enable this option to force use ADC2 under above conditions.
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For more details, you can search for errata on espressif website.
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config ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
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depends on IDF_TARGET_ESP32C3
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bool "Force use ADC2 oneshot mode on ESP32C3"
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default n
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help
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On ESP32C3, ADC2 Digital Controller is not stable. Therefore,
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ADC2 oneshot mode is not suggested on ESP32C3
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If you stick to this, you can enable this option to force use ADC2 under above conditions.
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For more details, you can search for errata on espressif website.
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endmenu # ADC Configuration
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menu "SPI configuration"
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config SPI_MASTER_IN_IRAM
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bool "Place transmitting functions of SPI master into IRAM"
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default n
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select SPI_MASTER_ISR_IN_IRAM
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help
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Normally only the ISR of SPI master is placed in the IRAM, so that it
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can work without the flash when interrupt is triggered.
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For other functions, there's some possibility that the flash cache
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miss when running inside and out of SPI functions, which may increase
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the interval of SPI transactions.
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Enable this to put ``queue_trans``, ``get_trans_result`` and
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``transmit`` functions into the IRAM to avoid possible cache miss.
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During unit test, this is enabled to measure the ideal case of api.
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config SPI_MASTER_ISR_IN_IRAM
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bool "Place SPI master ISR function into IRAM"
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default y
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help
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Place the SPI master ISR in to IRAM to avoid possible cache miss.
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Also you can forbid the ISR being disabled during flash writing
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access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
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config SPI_SLAVE_IN_IRAM
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bool "Place transmitting functions of SPI slave into IRAM"
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default n
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select SPI_SLAVE_ISR_IN_IRAM
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help
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Normally only the ISR of SPI slave is placed in the IRAM, so that it
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can work without the flash when interrupt is triggered.
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For other functions, there's some possibility that the flash cache
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miss when running inside and out of SPI functions, which may increase
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the interval of SPI transactions.
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Enable this to put ``queue_trans``, ``get_trans_result`` and
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``transmit`` functions into the IRAM to avoid possible cache miss.
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config SPI_SLAVE_ISR_IN_IRAM
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bool "Place SPI slave ISR function into IRAM"
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default y
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help
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Place the SPI slave ISR in to IRAM to avoid possible cache miss.
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Also you can forbid the ISR being disabled during flash writing
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access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
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endmenu # SPI Configuration
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menu "TWAI configuration"
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config TWAI_ISR_IN_IRAM
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bool "Place TWAI ISR function into IRAM"
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default n
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help
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Place the TWAI ISR in to IRAM. This will allow the ISR to avoid
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cache misses, and also be able to run whilst the cache is disabled
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(such as when writing to SPI Flash).
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Note that if this option is enabled:
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- Users should also set the ESP_INTR_FLAG_IRAM in the driver
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configuration structure when installing the driver (see docs for
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specifics).
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- Alert logging (i.e., setting of the TWAI_ALERT_AND_LOG flag)
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will have no effect.
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config TWAI_ERRATA_FIX_BUS_OFF_REC
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bool "Add SW workaround for REC change during bus-off"
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depends on IDF_TARGET_ESP32
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default n
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help
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When the bus-off condition is reached, the REC should be reset to 0 and frozen (via LOM) by the
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driver's ISR. However on the ESP32, there is an edge case where the REC will increase before the
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driver's ISR can respond in time (e.g., due to the rapid occurrence of bus errors), thus causing the
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REC to be non-zero after bus-off. A non-zero REC can prevent bus-off recovery as the bus-off recovery
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condition is that both TEC and REC become 0. Enabling this option will add a workaround in the driver
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to forcibly reset REC to zero on reaching bus-off.
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config TWAI_ERRATA_FIX_TX_INTR_LOST
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bool "Add SW workaround for TX interrupt lost errata"
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depends on IDF_TARGET_ESP32
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default n
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help
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On the ESP32, when a transmit interrupt occurs, and interrupt register is read on the same APB clock
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cycle, the transmit interrupt could be lost. Enabling this option will add a workaround that checks the
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transmit buffer status bit to recover any lost transmit interrupt.
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config TWAI_ERRATA_FIX_RX_FRAME_INVALID
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bool "Add SW workaround for invalid RX frame errata"
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depends on IDF_TARGET_ESP32
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default n
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help
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On the ESP32, when receiving a data or remote frame, if a bus error occurs in the data or CRC field,
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the data of the next received frame could be invalid. Enabling this option will add a workaround that
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will reset the peripheral on detection of this errata condition. Note that if a frame is transmitted on
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the bus whilst the reset is ongoing, the message will not be receive by the peripheral sent on the bus
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during the reset, the message will be lost.
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config TWAI_ERRATA_FIX_RX_FIFO_CORRUPT
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bool "Add SW workaround for RX FIFO corruption errata"
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depends on IDF_TARGET_ESP32
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default n
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help
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On the ESP32, when the RX FIFO overruns and the RX message counter maxes out at 64 messages, the entire
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RX FIFO is no longer recoverable. Enabling this option will add a workaround that resets the peripheral
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on detection of this errata condition. Note that if a frame is being sent on the bus during the reset
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bus during the reset, the message will be lost.
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config TWAI_ERRATA_FIX_LISTEN_ONLY_DOM
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bool "Add SW workaround for listen only transmits dominant bit errata"
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depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3
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default n
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help
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When in the listen only mode, the TWAI controller must not influence the TWAI bus (i.e., must not send
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any dominant bits). However, while in listen only mode on the ESP32/ESP32-S2/ESP32-S3/ESP32-C3, the
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TWAI controller will still transmit dominant bits when it detects an error (i.e., as part of an active
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error frame). Enabling this option will add a workaround that forces the TWAI controller into an error
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passive state on initialization, thus preventing any dominant bits from being sent.
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endmenu # TWAI Configuration
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menu "UART configuration"
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config UART_ISR_IN_IRAM
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bool "Place UART ISR function into IRAM"
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default n
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help
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If this option is not selected, UART interrupt will be disabled for a long time and
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may cause data lost when doing spi flash operation.
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endmenu # UART Configuration
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menu "RTCIO configuration"
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visible if IDF_TARGET_ESP32
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config RTCIO_SUPPORT_RTC_GPIO_DESC
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bool "Support array `rtc_gpio_desc` for ESP32"
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depends on IDF_TARGET_ESP32
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default n
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help
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The the array `rtc_gpio_desc` will don't compile by default.
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If this option is selected, the array `rtc_gpio_desc` can be compile.
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If user use this array, please enable this configuration.
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endmenu # RTCIO Configuration
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menu "GPIO Configuration"
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visible if IDF_TARGET_ESP32
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config GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
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bool "Support light sleep GPIO pullup/pulldown configuration for ESP32"
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depends on IDF_TARGET_ESP32
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help
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This option is intended to fix the bug that ESP32 is not able to switch to configured
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pullup/pulldown mode in sleep.
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If this option is selected, chip will automatically emulate the behaviour of switching,
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and about 450B of source codes would be placed into IRAM.
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endmenu # GPIO Configuration
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endmenu # Driver configurations
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