Acquires PM_APB_FREQ_MAX lock when carrying any transaction on I2S if
Power Management Framework is enabled.
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
Acquires PM_APB_FREQ_MAX lock when carrying any transaction on I2C if
Power Management Framework is enabled.
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
There are lot of prints of `Allocate TX buffer for DMA`
Changed these from `ESP_LOGI` to `ESP_LOGD`
Signed-off-by: Vikram Dattu <vikram.dattu@espressif.com>
The requirements of pin capabilites is different for spi master and
slave. The master needs CS, SCLK, MOSI to be output-able, while slave
needs MISO to be output-able.
Previous code is for master only.
This commit allows to place other 3 pins than MISO on input-only pins
for slaves. Refactoring for spi_common is also included.
Resolves https://github.com/espressif/esp-idf/issues/2455
1. Add missing get function to RMT API: rmt_get_idle_level().
2. Suppress error message from rmt_wait_tx_done() if wait_time==0 (allows for polling).
3. Remove the blank lines between parameter lists.
Merges https://github.com/espressif/esp-idf/pull/2666
closes https://github.com/espressif/esp-idf/issues/2494
closes https://github.com/espressif/esp-idf/pull/2493
closes https://github.com/espressif/esp-idf/pull/2496
1. Change bus reset to handle interrupted READ sequences.
2. Slow down I2C to 100khz during reset
3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
I am stealing this delay coding from @jeremyherbert #2493 pr.
2. Change Bus Reset to handle interrupted READ sequences.
The current code does not handle interrupted READ cycles.
If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.
The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH.
So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
3. fix typo
correct `sda_id` to `sda_io` in `i2c_master_clear_bus()` @ryan-ma found it. This typo was generated when I manually edited this patch on GitHub, I should have done a Copy/Paste operation!
It has been observed that, in case of underflow (data unavailability) in
I2S transmission, previously filled up tx descriptors continue to get
transmitted on line, causing noise in case of audio use case.
This change adds optional `tx_desc_auto_clear` field during I2S driver intialization
than can zero initialize tx descriptor in case of underflow situation in
interrupt handler itself.
Closes: https://github.com/espressif/esp-idf/issues/1789
(cherry picked from commit 765bf674d0)
Introduced in 9c23b8e5 and 4f87a62f. To get higher speed, menuconfig
options are added to put ISR and other functions into the IRAM. The
interrupt flag ESP_INTR_FLAG_IRAM is also mistakenly set when the ISR is
put into the IRAM. However callbacks, which are wrote by the user, are
called in the master and slave ISR. The user may not be aware of that
these callbacks are not disabled during flash operations. Any cache miss
during flash operation will cause panic.
Essentially IRAM functions and intrrupt flag ESP_INTR_FLAG_IRAM are
different, the latter means not disabling the ISR during flash
operations. New bus_config flag intr_flags is offered to help set the
interrupt attribute, including priority level, SHARED, IRAM (not
disabled during flash operations). It introduced a small BREAK to
IDFv3.1 (but the same as IDFv3.0) that the user has to manually set IRAM
flag now (therefore he's aware of the IRAM thing) to void the ISR being
disabled during flash operations.
This commit resolves a blocking in esp_aes_block function.
Introduce:
The problem was in the fact that AES is switched off at the moment when he should give out the processed data. But because of the disabled, the operation can not be completed successfully, there is an infinite hang. The reason for this behavior is that the registers for controlling the inclusion of AES, SHA, MPI have shared registers and they were not protected from sharing.
Fix some related issue with shared using of AES SHA RSA accelerators.
Closes: https://github.com/espressif/esp-idf/issues/2295#issuecomment-432898137
