Commit Graph

41 Commits

Author SHA1 Message Date
Marius Vikhammer
c7532e27fa fix(ulp-i2c): fixed ulp i2c not working from main cpu if compiled with 0S or O2
Compiler would optimize register write to use s8i which do not work for IO registers

Closes https://github.com/espressif/esp-idf/issues/12214
2023-09-13 11:47:36 +08:00
Jakob Hasse
a6cbf68991 compiler: replaced noreturn by __noreturn__ in header files
* noreturn may be replaced by third-party macros,
  rendering it ineffective

* Closes https://github.com/espressif/esp-idf/issues/11339
2023-05-18 12:49:40 +08:00
Sudeep Mohanty
08600cb1a3 ulp-riscv-i2c: Add ULP RISC-V I2C read/write timeout config option
The commit 88e4c06028 introduced a loop timeout for all ULP RISC-V I2C
transactions to avoid getting stuck in a forever loop. The loop timeout
was set to 500 msec by default. This commit improves on the concept by
making the loop timeout configurable via a Kconfig option in terms of
CPU ticks. If the timeout is set to -1 value then the transaction loops
will never timeout, therefore restoring the driver behavior before the
timeout was introduced.

The commit also updates the I2C Fast mode timings for esp32s2 which need
to be adjusted due to bus timing constraints.

Closes https://github.com/espressif/esp-idf/issues/11154
2023-05-09 15:07:50 +02:00
Marius Vikhammer
0bac174058 ulp: added sleep support for lp core
Added support for running LP core while hp core sleeps, as well
as waking up the hp core.
2023-04-27 09:51:41 +08:00
Sudeep Mohanty
88e4c06028 ulp-riscv-i2c: Updated ULP RISC-V I2C driver to abort when met with errors
The current ULP RISC-V RTC I2C driver got stuck in an infinite loop if
there is a I2C transaction error. This commit amends the driver flow to
abort the read/write operation if met with errors. It also adds a loop
timeout to avoid getting stuck in an infinite loop.The commit also
updates the default bus timing parameters for RTC I2C to be faster.
This commit also adds documentation help to guide users when they meet
with issues while working with the RTC I2C driver on the ULP RISC-V coprocessor.
2023-03-29 13:25:46 +02:00
Sudeep Mohanty
a67d15fdea ulp: Added APIs to handle ULP signal ISRs for the main CPU
This commit introduces APIs to handle ULP signal ISRs when the main core
is not in sleepmode.

Closes https://github.com/espressif/esp-idf/issues/10737
2023-02-24 07:25:39 +00:00
Sudeep Mohanty
3cc399f399 ulp-riscv: Added API ulp_riscv_reset to reset the ULP core
This commit adds a new API ulp_reisv_reset() to enable reseting of the
ULP core from the main core. This is particularly necessary in case the
ULP crashes due to any reason. Earlier the only way to recover the ULP
was to do a power reset. This commit also adds new test cases which
exercise this scenario.
2023-02-08 07:52:34 +00:00
Sudeep Mohanty
28ccb3b414 Merge branch 'bugfix/rtc_i2c_stuck_after_esp_restart' into 'master'
ulp risc-v rtc i2c: Fix a bug where RTC I2C failed to initialize after esp_restart()

Closes IDFGH-9065

See merge request espressif/esp-idf!21862
2023-01-05 15:59:08 +08:00
Sudeep Mohanty
2df00a4b17 Merge branch 'docs/ulp_riscv_i2c_sub_reg_addr' into 'master'
ulp-riscv-i2c: Updated API documentation about sub register address usage

Closes IDFGH-9023

See merge request espressif/esp-idf!21838
2023-01-05 15:58:29 +08:00
Sudeep Mohanty
4a410391cc ulp risc-v rtc i2c: Fix a bug where RTC I2C failed to initialize after esp_restart()
This commit fixes a bug wherein the RTC I2C peripheral got stuck after
the main CPU performs a soft reset by using esp_restart(). This is
because the RTC domain config registers for the RTC I2C domain are not
cleared after the soft restart and hence need to be cleared manually
while initializing the RTC I2C peripheral again.

Closes https://github.com/espressif/esp-idf/issues/10468
2023-01-02 15:44:03 +01:00
Sudeep Mohanty
07a506bb02 ulp-riscv-i2c: Updated API documentation about sub register address usage
The RTC I2C peripheral always expects a I2C slave sub register address
to be programmed. If it is not programmed then a sub register address
available in SENS_SAR_I2C_CTRL_REG[18:11] is used for I2C read/write.
This commit updates the documentation of the API
ulp_riscv_i2c_master_set_slave_reg_addr() to clarify the same.
2022-12-29 09:58:24 +01:00
Sudeep Mohanty
099f648686 ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2
This commit fixes an issue where in the ULP RISC-V I2C example causes
a spurious wakeup of the main CPU because of a Trap signal when the ULP
core does not meet the wakeup threshold values. This was due to the fact
that the RTC_CNTL_COCPU_DONE signal was being set before the
RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V
core to not reset properly on each cycle.

Closes https://github.com/espressif/esp-idf/issues/10301
2022-12-27 07:44:26 +00:00
KonstantinKondrashov
9fd8f3786a all: Replaces memset/memcpy with hal_mem.. funcs where were used -Wstringop-overread, -Wstringop-overflow, -Warray-bounds
hal: Adds hal_memcpy and hal_memset
2022-11-30 19:22:41 +08:00
Marius Vikhammer
7b5bdcf077 ulp-riscv: always force COCPU clock on S3
The coprocessor cpu trap signal doesnt have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU
2022-10-18 03:06:05 +00:00
Marius Vikhammer
77ba84eeb7 ulp-fsm: Update ulp-fsm ADC example with S3 support
Closes https://github.com/espressif/esp-idf/issues/7963
2022-09-07 16:48:06 +08:00
Sudeep Mohanty
4fde033a5f ulp: Added support for RTC I2C driver for ULP RISC-V on esp32s2 and esp32s3
This commit adds support for using the RTC I2C peripheral on the ULP
RISC-V core for esp32s2 and esp32s3. It also adds an example to demonstrate the
usage of the RTC I2C peripheral.

This commit also modifies the rtc_i2c register structure files to enable
the use of bitfields in the ULP RISC-V RTC I2C driver.
2022-09-05 10:21:43 +02:00
Marius Vikhammer
ffed60cc93 ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP. 2022-08-05 18:16:31 +08:00
Marius Vikhammer
035924a8f1 ulp: migrate tests to pytest embedded 2022-08-03 09:36:17 +08:00
Marius Vikhammer
5d23a757d6 Merge branch 'feature/ulp_uart' into 'master'
ulp-riscv: uart print

See merge request espressif/esp-idf!19229
2022-08-02 09:14:48 +08:00
Jiang Jiang Jian
b885499c74 Merge branch 'refactor/move_common_adc_part_to_hw_support' into 'master'
esp_adc: move esp_adc out of g1 dependency list

Closes IDF-5637

See merge request espressif/esp-idf!19159
2022-08-01 15:39:45 +08:00
Marius Vikhammer
af329784b1 ulp: fix missing cpp header guard
https://github.com/espressif/esp-idf/issues/9464
2022-08-01 10:19:32 +08:00
Marius Vikhammer
32efa1e92d Add ULP-RISCV print and bitbanged UART tx API
Add example to demonstrate the use of this API.
2022-07-29 12:18:01 +08:00
Armando
5e6a16380a esp_adc: move adc common hw related code into esp_hw_support 2022-07-28 03:49:48 +00:00
Marius Vikhammer
4f1046a292 ulp-riscv: made ulp_riscv_delay_cycles more accurate 2022-07-26 14:32:39 +08:00
Armando
5b523a3313 esp_adc: new esp_adc component and adc drivers 2022-07-15 18:31:00 +08:00
Marius Vikhammer
e8b5096f52 ulp-riscv: add support for using ADC as well as an example show-casing it. 2022-07-11 09:31:22 +08:00
Marius Vikhammer
6e79cc69f9 re-enable riscv ulp gpio support and examples
Closes https://github.com/espressif/esp-idf/issues/8691
Closes https://github.com/espressif/esp-idf/issues/9094
2022-06-08 17:59:28 +08:00
Marius Vikhammer
9c4a12b11e Revert "ulp: Keep RTC_CNTL_COCPU_SHUT_RESET_EN set for ULP RISC-V"
This reverts commit f709faea7c.
2022-06-08 17:59:07 +08:00
Anton Maklakov
6c30426777 ulp_riscv: suppress -Wstringop-overflow 2022-05-30 11:55:27 +07:00
Marius Vikhammer
c8617fe965 docs: fix all doxygen warnings
Doxygen warnings would previously not result in a failed pipeline.
Fixed this as well as all current warnings.
2022-05-12 14:50:03 +08:00
Sudeep Mohanty
f709faea7c ulp: Keep RTC_CNTL_COCPU_SHUT_RESET_EN set for ULP RISC-V
RTC_CNTL_COCPU_SHUT_RESET_EN register was being reset during ULP RISC-V
initialization which does not let the ULP RISC-V coprocessor to reset
after it goes to halt. For proper operation of the coprocessor, it must
be reset after each cycle and hence this commit keeps
RTC_CNTL_COCPU_SHUT_RESET_EN set.
2022-04-28 13:41:07 +05:30
Marius Vikhammer
2efd009dfb ulp: temporarily disable ULP support for S3
Due to a hardware issue ULP support on S3 is temporarily disabled until a fixed is released.
Running ULP + sleep together can potentially cause permanent damage to the chip.
2022-03-25 14:19:12 +08:00
Marius Vikhammer
c974a000d7 ULP: Add example of using GPIO to wakeup the ULP-RISCV processor 2022-02-28 14:15:25 +08:00
Marius Vikhammer
8a48b55197 ulp: change deprecated headers to use relative includes to avoid recursivly including the same header 2022-02-11 14:56:11 +08:00
Sudeep Mohanty
2fc9bd61bf ulp: refactor ulp component
This commit refactors the ulp component.
Files are now divided based on type of ulp, viz., fsm or risc-v.
Files common to both are maintained in the ulp_common folder.

This commit also adds menuconfig options for ULP within the ulp
component instead of presenting target specific configuations for ulp.
2022-01-27 11:54:42 +05:30
Marius Vikhammer
ff6f927b5f ULP: add functions for stopping/restarting the ulp-riscv
Closes https://github.com/espressif/esp-idf/issues/8232
2022-01-20 11:34:53 +08:00
Sudeep Mohanty
2ed15d8b1e ulp: Added ULP RISC-V support for esp32s3
This commit adds support for ULP RISC-V for esp32s3.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
2022-01-18 10:58:00 +05:30
Marius Vikhammer
386739595f RISCV-ULP: Add DS18B20 1wire RISCV-ULP example 2021-06-25 11:26:39 +08:00
Angus Gratton
3ee4370578 esp32s2 riscv ulp: Ensure reset vector is always at offset 0x0
Previous linker script relied on nothing else using the .text section

As reported at https://esp32.com/viewtopic.php?f=2&t=20734&p=75997
2021-05-06 09:25:32 +10:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
Felipe Neves
b6dba84323 ulp: added support to building code for riscv ULP coprocessor 2020-07-15 15:28:49 -03:00