Commit Graph

110 Commits

Author SHA1 Message Date
Omar Chebib
bc0b04d779 Merge branch 'staging/enabling_panic_test_esp32c61' into 'master'
test(panic): enable tests for esp32c61

Closes IDF-10994

See merge request espressif/esp-idf!33277
2024-09-10 11:37:38 +08:00
Alexey Lapshin
47212eaa3a feat(tools): update toolchain version to esp-14.2.0_20240903
Closes https://github.com/espressif/esp-idf/issues/13979
Closes https://github.com/espressif/esp-idf/issues/14273
Closes https://github.com/espressif/esp-idf/issues/14267
2024-09-08 13:52:22 +07:00
Omar Chebib
d025ff4073 test(panic): enable tests for esp32c61 2024-09-05 14:50:58 +08:00
Erhan Kurubas
1e3c3b8738 Merge branch 'feature/esp32c5_coredump' into 'master'
ESP32-C5 enable core dump tests

Closes IDF-8661

See merge request espressif/esp-idf!30151
2024-09-04 20:08:48 +08:00
wanckl
4e095f4b9f ci(esp32c61): enable c61 generic target test 2024-09-02 19:26:12 +08:00
Erhan Kurubas
23bc6eac43 test(coredump): enable esp32c5 coredump tests 2024-08-30 13:17:44 +03:00
Erhan Kurubas
3ef9750005 test(coredump): fix failed core dump tests 2024-08-28 11:12:39 +03:00
Jakob Hasse
d2cfb78d31 Merge branch 'refactor/spi_ram_stack_with_heap_caps_config' into 'master'
refactor(esp_psram): allow PSRAM as stack when PSRAM is only available via esp_heap_caps

Closes IDFGH-11604

See merge request espressif/esp-idf!32832
2024-08-20 16:48:44 +08:00
Jakob Hasse
0d32deb4c4 refactor(test_apps): increased timeout of panic tests 2024-08-15 16:16:54 +02:00
harshal.patil
14cbd837b3
ci(memprot): enable memory protection tests for ESP32-C5 2024-08-12 11:08:33 +05:30
Armando
7231a6388b feat(cache): supported cache panic on c61 2024-08-08 10:38:02 +08:00
Armando
564b74a9c0 feat(cache): supported cache panic on p4 2024-07-12 12:42:10 +08:00
harshal.patil
bd4e48d0d9
feat(cpu): Configure panic exception generation using asm illegal instruction 2024-06-25 11:55:24 +05:30
harshal.patil
a8f509f481
fix(esp_hw_support): Fix incorrect PMA configuration for ESP32-P4
- As the PMA entry that made some memory regions cacheable was
assigned the highest priority, some intermediate inaccessible
memory regions bypassed protection.

- Added tests for the same

- Verified that even after changing the priority of the PMA entry,
a write operation at SOC_IRAM_LOW + 0x40 (a random RAM cached address)
still needs the same number (29) of CPU cycles.
2024-06-10 11:55:58 +05:30
Erhan Kurubas
002faf3b0a ci(panic): extend extram_stack tests 2024-05-27 14:51:30 +02:00
Erhan Kurubas
55261747fc ci(panic): add coredump tcb corrupted test 2024-05-27 13:55:14 +02:00
Erhan Kurubas
8e524d708c fix(coredump): fix buffer overflow inside esp_core_dump_get_summary
Closes https://github.com/espressif/esp-idf/issues/13754
2024-05-07 06:49:28 +02:00
Erhan Kurubas
94fc3630f5 ci(panic): add flash encrypted coredump tests 2024-05-06 15:54:33 +02:00
Erhan Kurubas
551d91ea8a ci(coredump): fix capture dram tests 2024-05-06 15:43:43 +02:00
Konstantin Kondrashov
8b418d4b09 feat(esp_system): Print backtrace for both CPUs when cache error does not determine CPU 2024-04-30 15:20:58 +03:00
Erhan Kurubas
3b8191cf5d feat(coredump): save .bss, .data and .heap sections to the elf file 2024-04-23 19:07:51 +03:00
Alexey Lapshin
6f2de1fb23 fix(system): esp32p4: fix mepc when load/store failure occurred 2024-04-18 19:49:19 +04:00
Mahavir Jain
024b040300
test(memprot): enable memory protection tests for P4 2024-04-14 21:16:42 +05:30
Erhan Kurubas
483b4cd65b ci(coredump): enable custom stack tests for riscv chips 2024-04-09 13:36:30 +08:00
Kevin (Lao Kaiyao)
432864e917 Merge branch 'ci/enable_c5_mp_ci_jobs' into 'master'
ci(esp32c5mp): enable esp32c5 build on CI

See merge request espressif/esp-idf!29895
2024-04-08 12:16:16 +08:00
laokaiyao
65b1fd33d3 ci(esp32c5mp): disable the unsupported tests 2024-04-07 12:13:29 +08:00
Chen Yudong
7d13f8210f ci: fix pytest generic env markers 2024-04-03 18:10:43 +08:00
Laukik Hase
48503dd39f
fix(esp_hw_support): Fix the flash I/DROM region PMP protection 2024-04-02 18:41:07 +05:30
Alexey Lapshin
cb82161dae feat(system): esp32p4: support panic tests 2024-03-21 15:36:36 +04:00
Laukik Hase
2265c0f230
feat(tools/test_apps): Add violation tests for the flash I/DROM region
- For SoCs supporting PMP
2024-02-28 10:54:38 +05:30
Konstantin Kondrashov
d348258f2c fix(test_apps): Fix coredump_uart_bin_crc.test_hw_stack_guard_cpu0 test 2024-02-19 19:21:40 +08:00
Erhan Kurubas
f1d5f97719 feat(coredump): use SHA ROM functions for all targets except ESP32
For ESP32, continue using mbedtls due to a required ROM patch for the SHA implementation.
For other targets, we can now leverage the ROM functions.
2024-01-25 15:13:56 +01:00
Marius Vikhammer
297607587b test(panic): remove WDT both CPU test
Test never worked on S3/P4 and was flakey on ESP32. Hard to design a reliable test
case that triggers both WDT at the exact same time.
2024-01-23 11:55:18 +08:00
Marius Vikhammer
9f1d001849 Merge branch 'feat/cache_error_c6_h2' into 'master'
fix(panic): fixed cache error being reported as illegal instruction

Closes IDF-6398, IDF-5657, IDF-7015, and IDF-6733

See merge request espressif/esp-idf!27430
2023-12-21 10:32:06 +08:00
Erhan Kurubas
58ee206c99 feat(coredump): save twdt panic output to coredump elf file 2023-12-05 13:28:51 +01:00
Marius Vikhammer
9a6de4cb3e fix(panic): fixed cache error being reported as illegal instruction
On riscv chips accessing cache mapped memory regions over the ibus would
result in an illegal instructions exception triggering faster than the cache
error interrupt/exception.

Added a cache error check in the panic handler, if any cache errors are active
the panic handler will now report a cache error, even if the trigger exception
was a illegal instructions.
2023-12-04 10:49:00 +08:00
Darian Leung
a5d5ee7445 change(xtensa): Deprecate ".../xtensa_context.h" include path
This commit deprecates the "freertos/xtensa_context.h" and "xtensa/xtensa_context.h"
include paths. Users should use "xtensa_context.h" instead.

- Replace legacy include paths
- Removed some unnecessary includes of "xtensa_api.h"
- Add warning to compatibility header
2023-11-30 21:58:52 +08:00
Alexey Lapshin
fc7ac87b61 feat(tools): update gdb version to 12.1_20231023 2023-11-10 06:37:33 +00:00
Laukik Hase
3f67722274
refactor(tools/test_apps): Move HAL tests for MPU to the panic test-app 2023-10-13 10:16:57 +05:30
Alexey Lapshin
5c41edb863 fix(tools): fix panic test gcc 13.1.0 warnings 2023-10-09 12:13:02 +04:00
Erhan Kurubas
4714521b21 feat(coredump): add panic details to the elf file 2023-08-24 10:20:56 +02:00
Alexey Lapshin
4df3ff619e feat(esp_system): implement hw stack guard for riscv chips
- add hardware stack guard based on assist-debug module
- enable hardware stack guard by default
- disable hardware stack guard for freertos ci.release test
- refactor rtos_int_enter/rtos_int_exit to change SP register inside them
- fix panic_reason.h header for RISC-V
- update docs to include information about the new feature
2023-07-01 16:27:40 +00:00
Martin Vychodil
65bc1ed055 System: remove digital-system reset within OS restart when Memprot on 2023-06-26 20:22:59 +02:00
Alexey Lapshin
96768d7596 test: panic: use gdb-no-python to have ability to send signals 2023-05-19 20:15:58 +08:00
KonstantinKondrashov
b605404b06 esp_app_format: IRAM space optimization 2023-05-17 23:40:59 +08:00
Jakob Hasse
620cc586a2 tools: setting components to main to reduce build time 2023-04-25 15:42:22 +08:00
Marius Vikhammer
edb2994da9 ci: disable test_dram_reg2_execute_violation on esp32s2 2023-04-25 09:57:23 +08:00
laokaiyao
1f84f6c6ed esp32h4: remove esp32h4 target from ci 2023-04-20 15:19:47 +08:00
Ivan Grokhotkov
35ea136d5a
newlib: implement fsync for the case of CONFIG_VFS_SUPPORT_IO=0
This feature allows calling fsync even if the vfs component is not
used.
The second part of the commit adds an fsync call in the panic test app
enabling it to be used over usb-serial-jtag.
2023-04-18 11:19:36 +02:00
Alexey Lapshin
2b6de209c8 tests: panic: add esp32c6 esp32h2 2023-04-10 17:49:51 +08:00