4 Commits

Author	SHA1	Message	Date
wanlei	bb5a95f1aa	soc: fix register header files not self-contain	2022-07-29 11:18:06 +08:00
SalimTerryLi	874a720286	soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one ... update all struct headers to be more "standardized": - bit fields are properly wrapped with struct - bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits - bit field should be uint32_t - typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199 added helper macros to force peripheral registers being accessed in 32 bitwidth added a check script into ci	2021-08-30 13:50:58 +08:00
Armando	b53a68bf70	spi: update spi_struct and spi_reg to 727	2021-04-27 11:11:00 +08:00
Angus Gratton	c29d93986d	soc: Add initial ESP32-C3 support ... From internal commit 7761d6e8	2020-11-30 11:12:56 +11:00