alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

spi: update spi_struct and spi_reg to 727

Browse Source
This commit is contained in:
Armando 2021-04-26 19:07:08 +08:00
parent fb1fd26caf
commit b53a68bf70
3 changed files with 18 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
components/soc/esp32c3/include/soc/spi_struct.h
View File

@ -18,7 +18,6 @@
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
union {

36
components/soc/esp32s3/include/soc/spi_reg.h
View File

@ -52,20 +52,20 @@ clock domain, which is only used in SPI master mode..*/
#define SPI_USR_ADDR_VALUE_S 0
#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */
/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
figured in CONF state..*/
#define SPI_WR_BIT_ORDER 0x00000003
#define SPI_WR_BIT_ORDER_M ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S))
#define SPI_WR_BIT_ORDER_V 0x3
#define SPI_WR_BIT_ORDER_S 25
/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */
#define SPI_WR_BIT_ORDER (BIT(26))
#define SPI_WR_BIT_ORDER_M (BIT(26))
#define SPI_WR_BIT_ORDER_V 0x1
#define SPI_WR_BIT_ORDER_S 26
/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
tate..*/
#define SPI_RD_BIT_ORDER 0x00000003
#define SPI_RD_BIT_ORDER_M ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S))
#define SPI_RD_BIT_ORDER_V 0x3
#define SPI_RD_BIT_ORDER_S 23
#define SPI_RD_BIT_ORDER (BIT(25))
#define SPI_RD_BIT_ORDER_M (BIT(25))
#define SPI_RD_BIT_ORDER_V 0x1
#define SPI_RD_BIT_ORDER_S 25
/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low. C
an be configured in CONF state..*/
@ -813,20 +813,6 @@ _vld is cleared by spi_trans_done..*/
#define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18))
#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1
#define SPI_DMA_SLV_SEG_TRANS_EN_S 18
/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving dat
a. 0: DMA RX FIFO is ready for receiving data..*/
#define SPI_DMA_INFIFO_FULL (BIT(1))
#define SPI_DMA_INFIFO_FULL_M (BIT(1))
#define SPI_DMA_INFIFO_FULL_V 0x1
#define SPI_DMA_INFIFO_FULL_S 1
/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */
/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data.
0: DMA TX FIFO is ready for sending data..*/
#define SPI_DMA_OUTFIFO_EMPTY (BIT(0))
#define SPI_DMA_OUTFIFO_EMPTY_M (BIT(0))
#define SPI_DMA_OUTFIFO_EMPTY_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_S 0
#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
@ -1740,7 +1726,7 @@ M. 0: XTAL CLK..*/
#define SPI_CLK_EN_S 0
#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xF0)
/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012290 ; */
/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2010110 ; */
/*description: SPI register version..*/
#define SPI_DATE 0x0FFFFFFF
#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S))

15
components/soc/esp32s3/include/soc/spi_struct.h
View File

@ -13,6 +13,7 @@
// limitations under the License.
#ifndef _SOC_SPI_STRUCT_H_
#define _SOC_SPI_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
@ -49,9 +50,9 @@ typedef volatile struct {
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
uint32_t reserved22 : 1; /*reserved*/
uint32_t rd_bit_order : 2; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
uint32_t reserved22 : 3; /*reserved*/
uint32_t rd_bit_order : 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
uint32_t wr_bit_order : 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
@ -195,9 +196,7 @@ typedef volatile struct {
} dout_mode;
union {
struct {
uint32_t outfifo_empty : 1; /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
uint32_t infifo_full : 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
uint32_t reserved2 : 16; /*reserved*/
uint32_t reserved0 : 18; /*reserved*/
uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
@ -366,7 +365,7 @@ typedef volatile struct {
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t data_buf[16]; /*SPI CPU-controlled buffer0*/
uint32_t data_buf[16];
uint32_t reserved_d8;
uint32_t reserved_dc;
union {
@ -420,4 +419,4 @@ extern spi_dev_t GPSPI3;
}
#endif
#endif /* _SOC_SPI_STRUCT_H_ */
#endif /*_SOC_SPI_STRUCT_H_ */