Commit Graph

47 Commits

Author SHA1 Message Date
Jan Brudný
325deed208 esp32: update copyright notice 2021-06-04 11:51:06 +02:00
KonstantinKondrashov
f35356f69d esp32/psram: ESP32-PICO-V3 does not have PSRAM and does not support external PSRAM 2021-05-04 10:49:25 +08:00
Omar Chebib
cd79f3907d gpio: Disable USB JTAG when setting pins 18 and 19 as GPIOs on ESP32C3
When `DIS_USB_JTAG` eFuse is NOT burned (`False`), it is not possible
to set pins 18 and 19 as GPIOs. This commit solves this by manually
disabling USB JTAG when using pins 18 or 19.
The functions shall use `gpio_hal_iomux_func_sel` instead of
`PIN_FUNC_SELELECT`.
2021-04-08 14:01:18 +08:00
Michael (XIAO Xufeng)
647dea9395 soc: combine xxx_caps.h into one soc_caps.h
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
2020-10-17 16:10:15 +08:00
KonstantinKondrashov
2373f115fc efuse/esp32: Expands PKG_VER from 3 bit to 4 bits
Closes: IDF-1919
2020-09-17 07:44:37 +00:00
Angus Gratton
c09fdc0b09 esp32: Use package identifier to look up SPI flash/PSRAM WP Pin, unless overridden
Allows booting in QIO/QOUT mode or with PSRAM on ESP32-PICO-V3 and
ESP32-PICO-V3-O2 without any config changes.

Custom WP pins (needed for fully custom circuit boards) should still be compatible.
2020-07-20 14:08:49 +08:00
chenjianqiang
e9dd4f283a feat(esp32): support for esp32-pico-v3-02 2020-07-20 12:21:32 +08:00
morris
458b14a8ea esp_rom: extract common efuse apis into esp_rom_efuse.h 2020-07-15 10:40:50 +08:00
morris
a4d0033c03 esp_rom: extract common GPIO apis into esp_rom_gpio.h 2020-07-07 11:40:19 +08:00
Michael (XIAO Xufeng)
6b337049fb spiram: fix the read id failure
The issue is caused by:
1. The disable_qio_mode inside read_id may have side effects.
2. read_id twice may have side effects.

Fix this issue by moving disable_qio_mode out of read_id and only do it
once before read_id. And retry read_id only when the first one is
failed.

Issue introduced in 3ecbb59c15.
2020-06-23 11:18:20 +08:00
chenjianqiang
3ecbb59c15 psram: fix 16mbit psram id read error 2020-06-05 21:06:21 +08:00
chenjianqiang
04781fb009 psram: improve 2T mode enable
1. recover psram bankswitch config
2. set 2T mode enable default config as n
3. remove PSRAM ID check
2020-03-25 18:39:50 +08:00
chenjianqiang
55a20033e7 bugfix(psram): support psram 2T mode to fix single bit error
1. add enable PSRAM 2T mode function
2. enable PSRAM 2T mode base on PSRAM ID
3. abort when himem and 2T mode are enabled meanwhile
4. set SPIRAM_2T_MODE as "y" by default and modify SPIRAM_BANKSWITCH_ENABLE as "n" by default
2020-03-25 18:29:32 +08:00
Michael (XIAO Xufeng)
748b79e94a ci: fix one ut issue when using Wrover-B module with newer ver of PSRAM
The workaround for PSRAM that will occupy an SPI bus is enabled only when:

1. used on 32MBit ver 0 PSRAM.
2. work at 80MHz.

The test used to only check 32MBit by the config option, but for PSRAM
on Wrover-B module seems to use a newer version of 32MBit PSRAM.  So it
expects the workaround to be enabled, but actually not.

This commit split the unit test into two parts:

1. check all SPI buses are available, for all configs except psram_hspi
and psram_vspi, run on regular runners (including Wrover and Wrover-B).
a hidden option is enabled so that the compiler knows it's not building
psram_hspi or psram_vspi.

2. check the specified bus are acquired, for config psram_hspi and
psram_vspi. This only run on special runner (legacy Wrover module).
2019-11-03 03:07:37 +00:00
Angus Gratton
496ede9bcd Merge branch 'master' into feature/esp32s2beta_merge 2019-10-15 14:59:27 +11:00
Michael (XIAO Xufeng)
afbe1ba878 spi: move deprecated functions into internal header
Resolves https://github.com/espressif/esp-idf/issues/4132
2019-10-08 11:51:39 +08:00
Roland Dobai
15857d9cbb Handle deprecated values in sdkconfig.defaults
The issue was pointed out also in
https://github.com/espressif/esp-idf/issues/4092
2019-10-02 16:29:25 +00:00
Angus Gratton
6990a7cd54 Merge branch 'master' into feature/esp32s2beta_update 2019-08-19 15:03:43 +10:00
chenjianqiang
74e2e46402 bugfix(flash): add spi dio address bitlen configure in psram init 2019-08-14 20:57:30 +08:00
Angus Gratton
04ae56806c Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 15:26:58 +10:00
Angus Gratton
24d26fccde Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 13:44:24 +10:00
Anton Maklakov
afbaf74007 tools: Mass fixing of empty prototypes (for -Wstrict-prototypes) 2019-08-01 16:28:56 +07:00
chenjianqiang
d77c74770a bugfix(flash): add flash config in app startup
We fixed some flash bugs in bootloader, but for the users used the old
vrsion bootloader, they can not fix these bugs via OTA, the solution is
add these updates in app startup.

These updates include:
1. SPI flash gpio matrix and drive strength configuration
2. SPI flash clock configuration
3. SPI flash read dummy configuration
4. SPI flash cs timing configuration
5. Update flash id of g_rom_flashchip
2019-07-18 14:40:59 +08:00
Wang Jia Lin
e2d1c6234f Merge branch 'bugfix/improve_flash_dio_read_timing' into 'master'
bugfix(flash): fix flash dio read mode configuration error on SPI0

See merge request idf/esp-idf!5086
2019-06-14 12:10:46 +08:00
Angus Gratton
ddbd09eb15 esp32/esp32s2beta: Extract common SPIRAM options into esp_commmon component 2019-06-11 13:07:37 +08:00
Angus Gratton
a0382de0ea Merge branch 'bugfix/psram_io_struct_uninitialized' into 'master'
Make sure the psram_io struct is initialized

See merge request idf/esp-idf!5147
2019-06-07 07:36:16 +08:00
Jeroen Domburg
2b7da2a245 Make unknown psram package version more obvious 2019-06-06 16:57:01 +08:00
Jeroen Domburg
ed17cbbb8a Make sure the psram_io struct is initialized
Closes https://github.com/espressif/esp-idf/issues/3591
2019-06-06 09:05:49 +08:00
Konstantin Kondrashov
399d2d2605 all: Using xxx_periph.h
Using xxx_periph.h in whole IDF instead of xxx_reg.h, xxx_struct.h, xxx_channel.h ... .

Cleaned up header files from unnecessary headers (releated to soc/... headers).
2019-06-03 14:15:08 +08:00
chenjianqiang
db138ae19b feat(psram): config SPI psram pins based on efuse value 2019-05-28 21:25:16 +08:00
chenjianqiang
d68f1907ef bugfix(flash): improve flash dio read timing
When flash work in DIO Mode, in order to ensure the fast read mode of flash
is a fixed value, we merged the mode bits into address part, and the fast
read mode value is 0 (the default value).
2019-05-28 14:51:04 +08:00
Roland Dobai
0ae53691ba Rename Kconfig options (components/esp32) 2019-05-21 09:09:01 +02:00
Wangjialin
448d32bc53 bugfix(psram): improve spi cs timing settings for psram
1. remove redundant SPI clock settings, use rom functions to set clock.
2. remove redundant SPI cs setup and hold settings.
3. for old 32Mbit psram, cs hold time must only be 0.5T due to the special driving mode.(cs_setup = 0; cs_hold = 0)
4. for new 64Mbit psram, cs hold time is recommended to be 2.5T. (cs_setup = 1, cs_setup_time = 0;cs_hold = 1, cs_hold_time = 1)
2019-04-09 11:24:10 +08:00
morris
c159984264 separate rom from esp32 component to esp_rom
1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
2019-03-21 18:51:45 +08:00
chenjianqiang
bd8733f74f feature(psram): add psram support for esp32-pico chip
1. esp32-pico use standard spi driver to access psram
2. for esp32-pico, flash and psram share the clock
3. for esp32-pico, psram cs io can be overwrite via menuconfig
2019-01-09 10:49:07 +08:00
chenjianqiang
a0beff99d2 bugfix(psram): fix psram size acquisition method
1. Use BIT[7:5] of EID to determine psram size
2. Add ID support for 16Mbit psram
3. Remove module reset on SPI1
4. Confirmed with the vendor that only the old 32Mbit psram need special clock timing. For other psram chips, we should use standard QPI mode.
2018-11-28 17:05:37 +08:00
Michael (XIAO Xufeng)
20a666fe03 esp32: support to use hspi to output clock for 4MB PSRAM
Resolves https://github.com/espressif/esp-idf/issues/2128.
2018-10-29 20:22:44 +08:00
Michael (XIAO Xufeng)
9b5d0f3322 spi: shown owner of spi host explicitly 2018-10-29 20:22:44 +08:00
chenjianqiang
a10b7e892c bugfix(psram): fix psram driver
1. remove use EID to distinguish psram voltage
2. 1V8 64Mbit psram and 3V3 64Mbit psram use the same psram driver(standard spi interface)
3. set cs hold time register as 1
2018-10-08 19:55:13 +08:00
Wangjialin
6e9c59bfc3 feature(psram): add support for 64MBit psram of 1.8v and 3.3v.
1. Add reading psram EID.
2. Configure different clock mode for different EID.
3. add API to get psram size and voltage.
4. Remove unnecessary VSPI claim.

For 32MBit@1.8V and 64MBit@3.3V psram, there should be 2 extra clock cycles after CS get high level.
For 64MBit@1.8 psram, we can just use standard SPI protocol to drive the psram. We also need to increase the HOLD time for CS in this case.

EID for psram:
32MBit 1.8v: 0x20
64MBit 1.8v: 0x26
64MBit 3.3v: 0x46
2018-07-10 14:24:59 +08:00
Angus Gratton
d775cc4c4c soc: Fix description of rtc_config_t.tieh, add macros
Usage of TIEH was correct but description had 1.8V & 3.3V backwards.

Add macro definitions for TIEH values to improve readability.
2018-05-25 14:58:37 +10:00
jack
c384fa2492 rename clock enable and reset bits for SPI modules
1.The names of clock enable and reset bits do not match with TRM, just rename them.
2018-05-14 16:45:03 +08:00
Wangjialin
b1dcb52fec feature(psram): configure flash and psram speed during runtime
1. Bootloader reads SPI configuration from bin header, so that the burning configuration can be different with compiling configuration.
2. Psram mode init will overwrite original flash speed mode, so that users can change psram and flash speed after OTA.
3. Flash read mode(QIO/DIO…) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
4. Add read flash ID function, and save flash ID in g_rom_flashchip
5. Set drive ability for all related GPIOs
6. Check raise VDDSDIO voltage in 80Mhz mode
7. Add check flash ID and update settings in bootloader
8. Read flash ID once and keep in global variable
9. Read flash image header once and reuse the result

Tested cases:
1. Test new and old version of bootloader
boot Flash 20M —> app Flash 80M + Psram 80M
boot Flash 40M —> app Flash 80M + Psram 80M
boot Flash 80M —> app Flash 80M + Psram 80M
boot Flash 20M —> app Flash 80M + Psram 40M
boot Flash 40M —> app Flash 80M + Psram 40M
boot Flash 80M —> app Flash 80M + Psram 40M
boot Flash 20M —> app Flash 40M + Psram 40M
boot Flash 40M —> app Flash 40M + Psram 40M
boot Flash 80M —> app Flash 40M + Psram 40M
2. Working after esp_restart reboot.
2018-04-20 20:51:44 +08:00
Jeroen Domburg
569bfad2e3 Fix the clock subsystem so it doesn't undo the weird condition spiram_psram.c jams the enable/reset bits of SPI3 in when 80MHz mode is selected anymore 2017-12-19 19:12:58 +08:00
Wangjialin
cea7dfbe90 psram: improve clock signal generation, increase drive strength
Also check the chip type when initializing.
2017-11-03 16:30:10 +08:00
Jeroen Domburg
6d95934a3c Make 80MHz PSRAM work as well, add testcase for weirdness reported on esp32 forums, clean up unused define in psram code 2017-09-14 10:47:44 +08:00
Jeroen Domburg
34372a091c Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00