- add hardware stack guard based on assist-debug module
- enable hardware stack guard by default
- disable hardware stack guard for freertos ci.release test
- refactor rtos_int_enter/rtos_int_exit to change SP register inside them
- fix panic_reason.h header for RISC-V
- update docs to include information about the new feature
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32h2
ESP32-C2 has a single group timer, thus it will use it for the interrupt watchdog,
which is more critical than the task watchdog. The latter is implement in
software thanks to the `esp_timer`component.
In C++20, using the result of an assignment to a 'volatile' value is
deprecated.
Breaking change: register "setter" or modification macros can no
longer be used as expressions.
Closes https://github.com/espressif/esp-idf/issues/9170
components/bt: Do not use feature: timer support isr dispatch method
disable controller after wake up finished.
protect critical section of power down
choose clk in sleep
components/coex: mac bb power down in light sleep
components/coex: Macro changed
components/os: protect reserved interrupt number
update phy to phy_version 300,6e46ba7,Jan 25 2021
some bugfix
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)
Closes https://jira.espressif.com:8443/browse/IDF-2092
