14 Commits

Author	SHA1	Message	Date
wuzhenghui	fd79c593fb	fix(ci): increase uart driver test memory leak threshold	2024-09-07 02:04:43 +08:00
Song Ruo Jing	e1f27d04ed	fix(uart): enable ci target test for uart for c5	2024-09-02 15:24:29 +08:00
Lou Tianhao	4393343ac9	fix(ci): some actions taken to pass ci	2024-08-29 14:15:41 +08:00
Song Ruo Jing	1171c3c281	fix(ci): enable gpio, uart target tests on esp32p4	2024-08-15 21:54:21 +08:00
gaoxu	cd9d8bf2e9	feat(uart): support uart on ESP32C61	2024-08-05 15:06:51 +08:00
laokaiyao	c731b099ee	remove(c5beta3): remove c5 beta3 doxy files	2024-06-17 12:02:15 +08:00
Song Ruo Jing	dca7c286d0	feat(uart): support uart module sleep retention on c6/h2/p4	2024-06-03 12:40:43 +08:00
Michael (XIAO Xufeng)	f251e32f48	feat(uart_test): add test case for uart tx blocked by auto-suspend	2024-04-05 03:01:24 +08:00
LiPeng	235bb6f294	fix(uart): Fixed issue that TX be blocked by auto-lightsleep	2024-04-05 03:01:24 +08:00
Song Ruo Jing	5276cd4f1d	refactor(uart): add support to be able to test LP_UART port ... Increase LP_UART_EMPTY_THRESH_DEFAULT value to 4. The original value could cause the FIFO become empty before filling next data into the FIFO when the buadrate is high. TX_DONE interrupt would raise before actual transmission complete in such case.	2024-02-07 14:37:48 +08:00
Armando	3c5a4f9e8a	ci(p4): added todo jira for disabled tests on p4	2024-01-04 09:36:38 +08:00
Armando	907b876354	ci(p4): temporarily disable failed ci tests on p4	2024-01-04 09:36:06 +08:00
Song Ruo Jing	ef281dff5a	fix(esp_driver_uart): always use heap_caps_malloc to malloc memory base on flags	2023-12-15 17:03:58 +08:00
Song Ruo Jing	6ad80f0332	refactor(uart): make uart driver as component, and fix astyle	2023-12-15 17:03:51 +08:00