Added component containg API that is able to correct raw ADC readings
into a voltage in mV. Also provided a helper function that combines
the process of getting the raw ADC1 reading then converting it to a
voltage in mV. In doing so, the adc1_get_voltage() function of the ADC
driver has been deprecated. Instead there is now adc1_get_raw to obtain
the raw ADC1 reading, and adc1_to_voltage() that gets the raw reading
and converts all in one function. Functions using the deprecated
adc1_get_voltage() have also been updated to use adc1_get_raw().
Conversion is based on ADC characteristics. The characteristics are based
on the ADC's v_ref, herefore the appropriate structure and functions have
been provided to obtain the ADC characteristics.
The existing ADC driver has also been modified by adding a function to
route the internal ADC reference voltage to a GPIO allowing users to measure
it manually.
Relevant documentation has also been updated
All peripheral clocks are default enabled after chip is powered on.
When CPU starts, if reset reason is CPU reset, disable those clocks
that are not enabled before reset. Otherwise, disable all those
useless clocks.
These peripheral clocks must be enabled when the peripherals are
initialized and disabled when they are deinitialized.
The code in xtensa_vectors.S did not handle XT_DEBUG_BACKTRACE
consistently: #if was used in one case, and #ifdef in another. This makes
the checks consistent, and also introduces a Kconfig option to enable
backtrace.
In some cases, xPortGetCoreID was not inlined, and ended up in flash.
Since this function is used in many situations when cache is disabled,
that caused exceptions. Adding IRAM attribute to fix that.
vfs_uart used same locks for read and write operations on a single UART.
If read operation was blocking (i.e. carried out via UART driver), the
lock was held by reading task until it received a line. During this time,
other tasks trying to write to the same UART would get blocked.
This change introduces separate read/write locks, and adds a test.
Another vfs_uart test if fixed (it was disabled since the
CONFIG_NEWLIB_STDOUT_ADDCR option was removed).
If two different types of SHA hashes were active in the hardware
concurrently, a race condition meant the SHA unit could be incorrectly
reset leading to all-zero results.
If scheduler switches cores in narrow window during esp_dport_access_stall_other_cpu_start(), could cause the stall
interrupt to occur on the running CPU - halting the CPU until WDT cleans up.
Related to https://github.com/espressif/esp-idf/issues/630
