1. Rename MACROs SYSTEM_WIFI_RST_EN register bit fields to be more recognizable
2. reset Bluetooth baseband and MAC bits to fix the issue of task watchdog triggered during controller initialization due to invalid hardware state
The change fixes thread-local-storage size by removing .srodata section
from it. It initially was included in TLS section by mistake.
The issue was found when stack size increased after building applications
with GCC-11.1 compiler. Stack size became bigger because some new data
appeared in .srodata. See more details here:
adce62f53d
The previously used splits between memory allocated for ROM code,
2nd stage bootloader and the app were somewhat safe and conservative.
This resulted in some space being unavailable for static allocation
in the app.
This commit increases the space available for static allocation to the
maximum possible amount.
1. Some of the ROM code static allocation is only used in UART/USB/SPI
download modes. This region ("shared buffers") has been placed at
the lower end of ROM memory area, to be reusable in flash boot
mode. The 2nd stage bootloader linker script is modified to "pack"
all sections exactly up to the end but with roughly 8K margin between
startup stacks.
2. Instead of calculating the sections placement and hardcoding the
addresses in the LD script again, rewrite it to calculate the
start address of each memory region automatically based on the
logic above.
3. Adjust the app memory layout (SRAM_IRAM_END) accordingly,
increasing the space available for static allocation.
Overall these changes increase the space available for static
allocation by about 78kB.
The downside of these changes is that the 2nd stage bootloader .data
segment is now directly adjacent to the startup stack on the PRO CPU.
Previously, there was effectively about 78kB of extra stack space for
the PRO CPU, before the stack would run into the data segment.
This bugfix contains 3 fixes:
1. .rtc_dummy section is removed (not needed for C3)
2. .rtc_text section is padded with 16B for possible CPU prefetch
3. .rtc_text section is aligned to 4B boundary to comply with PMS Memprot requirements
"can set sleep wake stub from stack in RTC RAM" would randomly fail on S3 due to stack overflow.
Fixed wrong usage of stack size and slightly increased it.
This commit removes the following critical nested macros as follows:
- portENTER_CRITICAL_NESTED()
- portEXIT_CRITICAL_NESTED()
They are replaced with portSET_INTERRUPT_MASK_FROM_ISR() and
portCLEAR_INTERRUPT_MASK_FROM_ISR() which are the proper FreeRTOS interfaces.
Created a portmacro_deprecated.h for each port to contain deprecated API
that were originally from portmacro.h
esp_restart()/panic_restart() never resets the Digital system (so far required only by the Memprot feature) as there's a typo in the corresponding #define:
it checks CONFIG_ESP_SYSTEM_CONFIG_MEMPROT_FEATURE instead of CONFIG_ESP_SYSTEM_MEMPROT_FEATURE.
Issue fixed.
IDF-4094
In 4972605, high-level interrupt handler hook was renamed from
ld_include_highint_hdl to ld_include_panic_highint_hdl. However the
change wasn't applied in GNU Make based build system. As a result,
the default interrupt handler was linked and features which depended
on the high-level interrupt didn't work.
Closes https://github.com/espressif/esp-idf/issues/7759
Closes https://github.com/espressif/esp-idf/issues/7447
There was race condition where interrupt entries set by APP cpu core
could have been cleared during PRO cpu startup.
This was observed while setting up "cache access error" interrupt in
SMP mode for ESP32-S3.
This fix allows to NOT modify or clear any entries set by other core
(APP or PRO) and thus avoiding any race conditions during startup code.
As branches/jumps on Xtensa have a maximum range for the destination, it is
unsafe to refer to a label to another compilation unit in a branch/jump instruction.
The labels have been replaced by absolute addresses.
