62 Commits

Author	SHA1	Message	Date
Angus Gratton	6b57f33858	Merge branch 'refactor/movements_from_target_components' into 'master' ... Movement from target components 1 See merge request espressif/esp-idf!12482	2021-04-05 02:37:21 +00:00
Renz Bagaporo	301c48b6b2	esp_system: remove duplicate panic backtrace code	2021-04-01 07:22:57 +00:00
Renz Bagaporo	7d85c42e52	esp32: move brownout and cache err int setup	2021-03-31 19:13:03 +08:00
Renz Bagaporo	1efdcd69d9	xtensa: move out trax	2021-02-26 19:45:48 +08:00
Renz Bagaporo	7e0e91bf76	arch: move debug helpers	2021-02-26 13:34:29 +08:00
Renz Bagaporo	91a5770fd2	arch: move shared stack implementation to esp_system	2021-02-26 13:34:29 +08:00
Martin Vychodil	69096ddce5	Security: ESP32C3 memory protection feature (IRAM0/DRAM0) ... Software support for PMS module. Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W) On/locked by default, configurable in Kconfig (esp_system) Closes https://jira.espressif.com:8443/browse/IDF-2092	2021-01-27 08:44:03 +01:00
Konstantin Kondrashov	d23c7690f2	esp32c3: Add UTs for reset_reason	2021-01-18 07:12:21 +08:00
Omar Chebib	c218f669ba	panic on RISC-V: Take into account Merge Request comments	2020-12-31 15:46:17 +08:00
Omar Chebib	b6a450f824	panic: Add support for SoC-level panic ... SoC level exceptions such as watchdog timer and cache errors are now supported. Such exceptions now triggers a panic, giving more information about how and when it happened.	2020-12-31 15:46:17 +08:00
Renz Bagaporo	4cc6b5571b	esp_system: support riscv panic	2020-11-13 07:49:11 +11:00
Angus Gratton	420aef1ffe	Updates for riscv support ... * Target components pull in xtensa component directly * Use CPU HAL where applicable * Remove unnecessary xtensa headers * Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no longer signed/unsigned int). Changes come from internal branch commit a6723fc	2020-11-13 07:49:11 +11:00