Commit Graph

7 Commits

Author SHA1 Message Date
Marius Vikhammer
41d39a419f fix(pmp): fixed alignment of PMP addr for RTC mem on C5
Also refactored it for C6/H2/C61 to keep the approach consistent between targets
2024-07-04 16:24:46 +08:00
harshal.patil
84afc6a955
feat(esp_hw_support): Support memory protection using PMA and PMP for ESP32-C5 2024-06-25 11:55:15 +05:30
laokaiyao
21f870ecd5 remove(c5beta3): remove c5 beta3 system files 2024-06-17 12:02:15 +08:00
laokaiyao
01e3c85322 refactor(esp32c5): change beta3 path in esp_system and bootloader 2024-03-01 11:12:36 +08:00
Alexey Lapshin
824c8e0593 feat(esp_system): allow .bss to spill over into L2MEM above 0x4ff40000
This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:

- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
  SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data

If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):

  .dram0.bss (NOLOAD) :
  {
    arrays[dram0_bss]
    mapping[dram0_bss]
  } > sram_low

  .dram1.bss (NOLOAD) :
  {
    /* do not place here arrays[dram0_bss] because it may be splited
     * between segments */
    mapping[dram0_bss]
  } > sram_high
2024-02-28 19:41:25 +04:00
laokaiyao
d0a8f3e5c4 feat(esp32c5): support esptool on esp32c5 beta3 2024-01-09 13:11:11 +08:00
laokaiyao
11e19f40b9 feat(esp32c5): support to build hello world on esp32c5 beta3 2024-01-09 13:11:11 +08:00