The commit 88e4c06028 introduced a loop timeout for all ULP RISC-V I2C
transactions to avoid getting stuck in a forever loop. The loop timeout
was set to 500 msec by default. This commit improves on the concept by
making the loop timeout configurable via a Kconfig option in terms of
CPU ticks. If the timeout is set to -1 value then the transaction loops
will never timeout, therefore restoring the driver behavior before the
timeout was introduced.
The commit also updates the I2C Fast mode timings for esp32s2 which need
to be adjusted due to bus timing constraints.
Closes https://github.com/espressif/esp-idf/issues/11154
The current ULP RISC-V RTC I2C driver got stuck in an infinite loop if
there is a I2C transaction error. This commit amends the driver flow to
abort the read/write operation if met with errors. It also adds a loop
timeout to avoid getting stuck in an infinite loop.The commit also
updates the default bus timing parameters for RTC I2C to be faster.
This commit also adds documentation help to guide users when they meet
with issues while working with the RTC I2C driver on the ULP RISC-V coprocessor.
This commit adds a new API ulp_reisv_reset() to enable reseting of the
ULP core from the main core. This is particularly necessary in case the
ULP crashes due to any reason. Earlier the only way to recover the ULP
was to do a power reset. This commit also adds new test cases which
exercise this scenario.
This commit fixes a bug wherein the RTC I2C peripheral got stuck after
the main CPU performs a soft reset by using esp_restart(). This is
because the RTC domain config registers for the RTC I2C domain are not
cleared after the soft restart and hence need to be cleared manually
while initializing the RTC I2C peripheral again.
Closes https://github.com/espressif/esp-idf/issues/10468
The RTC I2C peripheral always expects a I2C slave sub register address
to be programmed. If it is not programmed then a sub register address
available in SENS_SAR_I2C_CTRL_REG[18:11] is used for I2C read/write.
This commit updates the documentation of the API
ulp_riscv_i2c_master_set_slave_reg_addr() to clarify the same.
This commit fixes an issue where in the ULP RISC-V I2C example causes
a spurious wakeup of the main CPU because of a Trap signal when the ULP
core does not meet the wakeup threshold values. This was due to the fact
that the RTC_CNTL_COCPU_DONE signal was being set before the
RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V
core to not reset properly on each cycle.
Closes https://github.com/espressif/esp-idf/issues/10301
This commit adds support for using the RTC I2C peripheral on the ULP
RISC-V core for esp32s2 and esp32s3. It also adds an example to demonstrate the
usage of the RTC I2C peripheral.
This commit also modifies the rtc_i2c register structure files to enable
the use of bitfields in the ULP RISC-V RTC I2C driver.
RTC_CNTL_COCPU_SHUT_RESET_EN register was being reset during ULP RISC-V
initialization which does not let the ULP RISC-V coprocessor to reset
after it goes to halt. For proper operation of the coprocessor, it must
be reset after each cycle and hence this commit keeps
RTC_CNTL_COCPU_SHUT_RESET_EN set.
Due to a hardware issue ULP support on S3 is temporarily disabled until a fixed is released.
Running ULP + sleep together can potentially cause permanent damage to the chip.
This commit refactors the ulp component.
Files are now divided based on type of ulp, viz., fsm or risc-v.
Files common to both are maintained in the ulp_common folder.
This commit also adds menuconfig options for ULP within the ulp
component instead of presenting target specific configuations for ulp.
