Commit Graph

18 Commits

Author SHA1 Message Date
wangmengyang
1d55f12c2d component/bt: reset Bluetooth hardware during controller inititalization on ESP32-C3/ESP32-S3
1. Rename MACROs SYSTEM_WIFI_RST_EN register bit fields to be more recognizable
2. reset Bluetooth baseband and clock bits to fix the issue of task watchdog triggered during controller initialization due to invalid hardware state
2022-07-06 16:23:48 +08:00
Michael (XIAO Xufeng)
7b8e5888ca Merge branch 'refactor/add_clk_tree_ll' into 'master'
clk_tree: Stage3 - HAL for clock subsystem

Closes IDF-4334

See merge request espressif/esp-idf!18270
2022-06-14 17:16:29 +08:00
songruojing
03477a59db rtc_clk: Fix rtc8m calibration failure after cpu/core reset
1. make sure 8md256 clk is enabled before calibration
2. improve bootloader and application startup 8m, 8md256 enable logic
2022-06-13 17:47:51 +08:00
KonstantinKondrashov
46f0313d6b reset_reasons: EFUSE_RST is treated as POWERON_RST
ESP32 does not have the EFUSE_RST, the rest chips has this reset reason.
2022-06-09 17:49:03 +08:00
KonstantinKondrashov
ac4c7d99fe dport: Move DPORT workaround to G0 2022-05-31 13:44:18 +08:00
songruojing
a5b09cf015 rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in
soc/clk_tree_defs.h
2022-05-24 22:59:41 +08:00
Marius Vikhammer
d2872095f9 soc: moved kconfig options out of the target component.
Moved the following kconfig options out of the target component:
 * CONFIG_ESP*_DEFAULT_CPU_FREQ* -> esp_system
 * ESP*_REV_MIN -> esp_hw_support
 * ESP*_TIME_SYSCALL -> newlib
 * ESP*_RTC_* -> esp_hw_support

Where applicable these target specific konfig names were merged into
a single common config, e.g;
CONFIG_ESP*_DEFAULT_CPU_FREQ -> CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
2022-04-21 12:09:43 +08:00
Marius Vikhammer
ca3c056ac9 kconfig: replace deprecated options with new values 2022-03-15 16:28:53 +08:00
songruojing
c1dedb33fa esp_system: replace the range comparsion for reset reason in perip clk init with specific reset reason check, also add a test case in LEDC to check for the perip clk not being disabled after cpu reset 2022-02-09 15:54:34 +08:00
Cao Sen Miao
eddc196081 esp_clk: refactor target/clk.h to private/esp_clk.h 2021-11-26 14:56:30 +08:00
morris
16677b0d3c global: make periph enable/disable APIs private
peripheral enable/disable usually should be managed by driver itself,
so make it as espressif private APIs, not recommended for user to use it
in application code.
However, if user want to re-write the driver or ports to other platform,
this is still possible by including the header in this way:
"esp_private/peripheral_ctrl.h"
2021-11-08 10:37:47 +08:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
Michael (XIAO Xufeng)
a0d13a31ec uart: fix misleading files for UART2
Includes: header files, ld files and clk.c

ESP32-C3 only have UART0 and UART1.
2021-04-27 17:40:19 +08:00
KonstantinKondrashov
aa1338bf23 wdt: Fix timeout and RTC_SLOW_CLK
RTC_SLOW_CLK
ESP32:    150kHz
ESP32-S2:  90kHz
ESP32-S3: 150kHz
ESP32-C3: 150kHz
2021-03-19 00:15:18 +08:00
Angus Gratton
d6f4d99d93 core system: Fix warnings in compilation when assertions are disabled
Adds a CI config for hello world that sets this, to catch future regressions
2021-03-03 10:26:57 +11:00
Michael (XIAO Xufeng)
d7d1dee208 system: reset dma when soft reset 2021-01-25 04:51:40 +00:00
KonstantinKondrashov
dada7cd035 global: Uses CCOUNT API instead of XTHAL macro 2021-01-12 16:24:23 +08:00
Angus Gratton
61c77d9212 esp_system: Add port-specific esp32c3 files 2020-12-24 13:40:01 +11:00