Marius Vikhammer
|
ff6f927b5f
|
ULP: add functions for stopping/restarting the ulp-riscv
Closes https://github.com/espressif/esp-idf/issues/8232
|
2022-01-20 11:34:53 +08:00 |
|
Sudeep Mohanty
|
2ed15d8b1e
|
ulp: Added ULP RISC-V support for esp32s3
This commit adds support for ULP RISC-V for esp32s3.
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
|
2022-01-18 10:58:00 +05:30 |
|
Marius Vikhammer
|
386739595f
|
RISCV-ULP: Add DS18B20 1wire RISCV-ULP example
|
2021-06-25 11:26:39 +08:00 |
|
Angus Gratton
|
3ee4370578
|
esp32s2 riscv ulp: Ensure reset vector is always at offset 0x0
Previous linker script relied on nothing else using the .text section
As reported at https://esp32.com/viewtopic.php?f=2&t=20734&p=75997
|
2021-05-06 09:25:32 +10:00 |
|
Angus Gratton
|
66fb5a29bb
|
Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.
(Line endings, blank lines at end of file, trailing whitespace)
|
2020-11-11 07:36:35 +00:00 |
|
Felipe Neves
|
b6dba84323
|
ulp: added support to building code for riscv ULP coprocessor
|
2020-07-15 15:28:49 -03:00 |
|