This commit enables ULP FSM support for esp32s3 and updates ULP FSM code
flow for other chips.
It adds C Macro support for the ULP FSM instruction set on esp32s2 and
esp32s3.
The unit tests are also updated to test ULP FSM on ep32s2 and esp32s3.
When compiling
> const ulp_insn_t program[] = {
> I_DELAY(1)
> };
with the xtensa-esp32-elf-g++ compiler i always got the error:
> sorry, unimplemented: non-trivial designated initializers not supported
>
> };
This was due to the different order in the macro and the struct. The struct has another order of the fields (opcode, unused, cycles) vs (cycles, unused, opcode):
> struct {
> uint32_t cycles : 16; /*!< Number of cycles to sleep */
> uint32_t unused : 12; /*!< Unused */
> uint32_t opcode : 4; /*!< Opcode (OPCODE_DELAY) */
> } delay; /*!< Format of DELAY instruction */
After updating the order in the macro it is possible to compile with the g++ compiler.
Merges https://github.com/espressif/esp-idf/pull/1310
This fixes incorrect descriptions of I_END/I_SLEEP instructions and
changes the definition of I_END. New instruction, I_WAKE, is added,
which wakes up the SoC. Macro for ADC instruction is defined, and new
tests are added.
- I_RD_REG used the wrong union member (.rd_reg) due to a copy-paste
mistake
- Peripheral register address in bits[7:0] should be given in words,
not in bytes
Fixes https://github.com/espressif/esp-idf/issues/297
Starting the ULP using SENS_SAR_START_FORCE_REG doesn’t disable clock gating of RTC fast clock.
When SoC goes into deep sleep mode, RTC fast clock gets gated, so ULP can no longer run.
Instead, it has to be started using the timer (RTC_CNTL_ULP_CP_SLP_TIMER_EN bit).
When ULP is enabled by the timer, clock also gets enabled.
