Commit Graph

135 Commits

Author SHA1 Message Date
Song Ruo Jing
707aebc607 feat(uart): support uart module sleep retention on c6/h2 2024-06-18 15:04:20 +08:00
Omar Chebib
742b3a1814 fix(esp_hw_support): clear reserved interrupts that are not applicable for each target 2024-05-30 12:12:44 +08:00
Omar Chebib
35dd4e1557 refactor(esp_hw_support): changed reserved interrupt functions to be now defined per SoC 2024-05-30 11:49:13 +08:00
Li Shuai
9c8b54b886 change(esp_hw_support): use new retention api to implement gdma retention 2024-04-22 12:49:33 +08:00
wuzhenghui
8f896f07c5
fix(esp_hw_support): fix pmu power domain initialize order 2024-04-10 10:10:13 +08:00
Laukik Hase
17ffe58051
fix(esp_hw_support): Fix the flash I/DROM region PMP protection 2024-04-03 15:48:46 +05:30
hongshuqing
7771d72d7c fix: fix_maximum_value_of_config_rtc_clk_cal_cycle_bug 2024-03-14 16:11:20 +08:00
Laukik Hase
68442ecaa0
refactor(esp_hw_support): Remove redundant PMP entry for ROM region
- The ROM text and data sections share the address range
    (see SOC_I/DROM_MASK_LOW - SOC_I/DROM_MASK_HIGH).
  - Initially, we had two PMP entries for this address range - one marking the
    region as RX and the other as R.
  - However, the latter entry is redundant as the former locks the PMP settings.
  - We can divide the ROM region into text and data sections later when we
    define boundaries marking these regions from the ROM.
2024-03-01 10:25:07 +05:30
Laukik Hase
a56fc41215
fix(esp_hw_support): Fix the I/DCACHE region PMP protection 2024-03-01 10:25:07 +05:30
Jiang Jiang Jian
3c7c5829b7 Merge branch 'h2_auto_dbias_master_hsq_v5.2' into 'release/v5.2'
ESP32H2: Active & sleep dbias get from efuse to fix the voltage (v5.2)

See merge request espressif/esp-idf!28714
2024-02-21 10:49:16 +08:00
wuzhenghui
2cd8335818
feat(esp_hw_support): support gdma register context sleep retention 2024-02-18 15:57:15 +08:00
Mahavir Jain
e173895618 fix(soc): change debug addr range to CPU subsystem range
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
2024-01-29 13:57:04 +08:00
hongshuqing
9373d53ce7 feat(pmu): set fix voltage to different mode for esp32h2
h2 remove include
2024-01-26 11:36:57 +08:00
Michael (XIAO Xufeng)
e1dfdf26bc Merge branch 'bugfix/recalib_bbpll_before_tuning_v5.2' into 'release/v5.2'
fix(bbpll): fix bbpll may not lock or not stable bug for stop early (ESP32C2/S3/C6/H2) (v5.2)

See merge request espressif/esp-idf!28284
2024-01-17 21:30:10 +08:00
Lou Tianhao
745a1f492e feat(pm): support PMU trigger regdma when PU TOP 2024-01-08 21:23:28 +08:00
Xiao Xufeng
ea45c22a5c fix(rtc): fixed bbpll not calibrated from bootloader issue 2024-01-05 10:24:49 +08:00
chaijie@espressif.com
016b63dacf fix(bbpll): fix bbpll calibration may stop early bug(ESP32C2/S3/C6/H2) 2024-01-05 03:22:44 +08:00
Marius Vikhammer
b5785b41eb docs(esp32p4): update misc docs for esp32p4 2024-01-03 18:26:55 +08:00
wuzhenghui
83b6c79f93
fix(esp_hw_support/sleep): wait flash ready after non-pd_top lightsleep for esp32c6 2023-12-27 15:34:55 +08:00
wuzhenghui
7b3c08e37a
fix(esp_hw_support/sleep): fix rtc_time_us_to_slowclk div zero in deepsleep process
Closes https://github.com/espressif/esp-idf/issues/12695
2023-12-08 13:59:52 +08:00
Jakob Hasse
e3653aaa98 fix(esp_hw_support): Removed unused include directories from cmake
* Closes https://github.com/espressif/esp-idf/issues/12700
2023-12-04 12:59:51 +08:00
Li Shuai
2a968da432 change(Power Management): the xpd_xtal32k value depends on system slow clock source config option when pmu initialize 2023-11-08 14:55:14 +08:00
zlq
9c2d470465 feat(bootloader): adjust dbias of bootloader, change clock of H2 to 64
MHz
2023-10-12 14:51:54 +08:00
Xiao Xufeng
28ba080c5e Revert "feat(volt): chip auto adjust volt for esp32c6 & esp32h2"
This reverts commit b221f87e00.
2023-10-12 14:51:54 +08:00
Lou Tian Hao
adae54faca Merge branch 'bringup/support_callback_mechanism_in_lightsleep_flow' into 'master'
Power Management: support_callback_mechanism_in_lightsleep_flow

Closes WIFI-5936

See merge request espressif/esp-idf!24597
2023-10-08 20:16:01 +08:00
gaoxu
8efe950077 fix(adc): power settings not taking into effect on H2 2023-09-28 17:41:42 +00:00
zlq
b221f87e00 feat(volt): chip auto adjust volt for esp32c6 & esp32h2 2023-09-28 05:55:42 +00:00
Kevin (Lao Kaiyao)
9a239b8367 Merge branch 'feature/support_analog_comparator_on_p4' into 'master'
feat(ana_cmpr): supported analog comparator on esp32p4

Closes IDF-7479

See merge request espressif/esp-idf!24873
2023-09-27 04:24:09 +08:00
Jiang Jiang Jian
2ec907e621 Merge branch 'bugfix/fix_sleep_risk_vol_param' into 'master'
bugfix(sleep): fix risk sleep vol param for esp32c6 & esp32h2

See merge request espressif/esp-idf!25993
2023-09-26 14:06:56 +08:00
laokaiyao
ff7a11e539 feat(ana_cmpr): supported etm in analog comparator example 2023-09-25 19:57:34 +08:00
chaijie@espressif.com
76aca4cc8a fix(sleep): fix inproper sleep vol param for esp32c6 & esp32h2 2023-09-25 16:37:35 +08:00
Lou Tianhao
450e685cb7 feat(PowerManagement/lightsleep): Support ESP_SLEEP_EVENT_CALLBACKS 2023-09-25 15:39:18 +08:00
harshal.patil
6a7caa7b8e
feat(esp_hw_support): Added locking mechanism for the ECDSA and ECC peripheral 2023-09-20 16:05:50 +05:30
morris
035c7c145c feat(clk_cali): always enable timer group0 for clock calibration
Calibration registers are located in the timer group0,
this commit is going to always enable it when the calibration is used by app
2023-08-22 17:05:35 +08:00
wuzhenghui
c34cdd05e9 fix(esp_hw_support): manage i2c_ana_mst clock witch modem clock driver 2023-08-04 10:39:43 +08:00
Lou Tianhao
7bd92287c4 change(pm/deepsleep): Update deep_sleep pmu analog parameter for esp32h2 2023-07-20 11:43:57 +08:00
Lou Tianhao
dcacd8cdf8 feat(pm/deepsleep): Support deep_sleep example and deep_sleep_wake_stub example for esp32h2 2023-07-20 11:43:57 +08:00
Mahavir Jain
6431091ce6
fix(esp32h2): correct typo in chip revision prompt 2023-07-18 20:46:45 +05:30
wuzhenghui
14ea226351 fix(rtc_clk): fix i2c master clock missing in bbpll configure 2023-07-13 14:07:35 +08:00
Li Shuai
f4c3b07436 fix(rtc_clk): fix the issue of missing configuration for calibration cycles of the internal 32 kHz RC 2023-07-04 11:23:07 +08:00
Lou Tianhao
6ee0f89676 Power Management: fix hp xtal wait bug for esp32h2 and esp32c6 2023-06-26 21:05:17 +08:00
Lou Tianhao
a329b15e7e Power Management: support pu xtal in light sleep for esp32h2 2023-06-26 21:05:16 +08:00
Lou Tianhao
ca55b91242 Power Management: update pmu init and sleep parameter 2023-06-26 21:05:16 +08:00
Lou Tianhao
46cf3ecdc2 Power Management: support PAU REGDMA feature for esp32h2 2023-06-26 20:58:59 +08:00
Lou Tianhao
63d32ab620 Power Management: support DFS and PMU feature for esp32h2 2023-06-26 20:57:55 +08:00
wuzhenghui
3ae1f0ea5d bugfix: fix rc_fast bad calibration value 2023-05-25 21:21:14 +08:00
zlq
ff88f42819 H2:fix tsensor issue @low temp 2023-05-09 19:40:53 +08:00
Wu Zheng Hui
35bb946653 Merge branch 'bugfix/update_esp32c6eco1_sleep_fosc_cal_cycles' into 'master'
bugfix: update esp32c6eco1 / esp32h2eco2 fosc calibration cycles during sleep and support calibrate OSC clock every N times lightsleep

Closes IDF-7287

See merge request espressif/esp-idf!23489
2023-05-09 18:44:20 +08:00
wuzhenghui
dd4d1bbe90 bugfix: fix esp32c6eco1 fosc calibration cycles during sleep 2023-05-04 11:46:21 +08:00
hongshuqing
430776fc46 fix wrong hp ldo for h2 2023-04-27 17:29:10 +08:00