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fix(esp_hw_support): manage i2c_ana_mst clock witch modem clock driver

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This commit is contained in:
wuzhenghui 2023-08-02 14:06:07 +08:00
parent d0fb902789
commit c34cdd05e9
6 changed files with 67 additions and 17 deletions
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12
components/esp_hw_support/modem_clock.c
View File

@ -277,15 +277,17 @@ void IRAM_ATTR modem_clock_module_mac_reset(periph_module_t module)
portEXIT_CRITICAL_SAFE(&ctx->lock);
}
#define WIFI_CLOCK_DEPS (BIT(MODEM_CLOCK_WIFI_MAC) | BIT(MODEM_CLOCK_FE) | BIT(MODEM_CLOCK_WIFI_BB) | BIT(MODEM_CLOCK_COEXIST))
#define BLE_CLOCK_DEPS (BIT(MODEM_CLOCK_BLE_MAC) | BIT(MODEM_CLOCK_FE) | BIT(MODEM_CLOCK_BLE_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST))
#define IEEE802154_CLOCK_DEPS (BIT(MODEM_CLOCK_802154_MAC) | BIT(MODEM_CLOCK_FE) | BIT(MODEM_CLOCK_BLE_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST))
#define COEXIST_CLOCK_DEPS (BIT(MODEM_CLOCK_COEXIST))
#define PHY_CLOCK_DEPS (BIT(MODEM_CLOCK_I2C_MASTER) | BIT(MODEM_CLOCK_FE))
#define WIFI_CLOCK_DEPS (BIT(MODEM_CLOCK_WIFI_MAC) | BIT(MODEM_CLOCK_WIFI_BB) | BIT(MODEM_CLOCK_COEXIST))
#define BLE_CLOCK_DEPS (BIT(MODEM_CLOCK_BLE_MAC) | BIT(MODEM_CLOCK_BLE_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST))
#define IEEE802154_CLOCK_DEPS (BIT(MODEM_CLOCK_802154_MAC) | BIT(MODEM_CLOCK_BLE_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST))
#define COEXIST_CLOCK_DEPS (BIT(MODEM_CLOCK_COEXIST))
#define PHY_CLOCK_DEPS (BIT(MODEM_CLOCK_I2C_MASTER) | BIT(MODEM_CLOCK_FE))
#define I2C_ANA_MST_CLOCK_DEPS (BIT(MODEM_CLOCK_I2C_MASTER))
static IRAM_ATTR uint32_t modem_clock_get_module_deps(periph_module_t module)
{
uint32_t deps = 0;
if (module == PERIPH_ANA_I2C_MASTER_MODULE) {deps = I2C_ANA_MST_CLOCK_DEPS;}
if (module == PERIPH_PHY_MODULE) {deps = PHY_CLOCK_DEPS;}
else if (module == PERIPH_COEX_MODULE) { deps = COEXIST_CLOCK_DEPS; }
#if SOC_WIFI_SUPPORTED

25
components/esp_hw_support/port/esp32c6/rtc_clk.c
View File

@ -17,10 +17,15 @@
#include "esp_rom_sys.h"
#include "hal/clk_tree_ll.h"
#include "hal/regi2c_ctrl_ll.h"
#include "hal/modem_lpcon_ll.h"
#include "soc/io_mux_reg.h"
#include "soc/lp_aon_reg.h"
#ifdef BOOTLOADER_BUILD
#include "hal/modem_lpcon_ll.h"
#else
#include "esp_private/esp_modem_clock.h"
#endif
static const char *TAG = "rtc_clk";
// Current PLL frequency, in 480MHz. Zero if PLL is not enabled.
@ -138,12 +143,25 @@ static void rtc_clk_bbpll_enable(void)
clk_ll_bbpll_enable();
}
static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
{
#ifdef BOOTLOADER_BUILD
modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable);
#else
if (enable) {
modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
} else {
modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
}
#endif
}
static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
{
/* Digital part */
clk_ll_bbpll_set_freq_mhz(pll_freq);
/* Analog part */
modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, true);
rtc_clk_enable_i2c_ana_master_clock(true);
/* BBPLL CALIBRATION START */
regi2c_ctrl_ll_bbpll_calibration_start();
clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@ -151,8 +169,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
/* BBPLL CALIBRATION STOP */
regi2c_ctrl_ll_bbpll_calibration_stop();
modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, false);
rtc_clk_enable_i2c_ana_master_clock(false);
s_cur_pll_freq = pll_freq;
}

25
components/esp_hw_support/port/esp32h2/rtc_clk.c
View File

@ -17,11 +17,16 @@
#include "esp_rom_sys.h"
#include "hal/clk_tree_ll.h"
#include "hal/regi2c_ctrl_ll.h"
#include "hal/modem_lpcon_ll.h"
#include "soc/io_mux_reg.h"
#include "soc/lp_aon_reg.h"
#include "soc/lp_clkrst_reg.h"
#ifdef BOOTLOADER_BUILD
#include "hal/modem_lpcon_ll.h"
#else
#include "esp_private/esp_modem_clock.h"
#endif
static const char *TAG = "rtc_clk";
// Current PLL frequency, in 96MHz. Zero if PLL is not enabled.
@ -155,12 +160,25 @@ static void rtc_clk_bbpll_enable(void)
clk_ll_bbpll_enable();
}
static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
{
#ifdef BOOTLOADER_BUILD
modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable);
#else
if (enable) {
modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
} else {
modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
}
#endif
}
static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
{
/* Digital part */
clk_ll_bbpll_set_freq_mhz(pll_freq);
/* Analog part */
modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, true);
rtc_clk_enable_i2c_ana_master_clock(true);
/* BBPLL CALIBRATION START */
regi2c_ctrl_ll_bbpll_calibration_start();
clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@ -168,8 +186,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
/* BBPLL CALIBRATION STOP */
regi2c_ctrl_ll_bbpll_calibration_stop();
modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, false);
rtc_clk_enable_i2c_ana_master_clock(false);
s_cur_pll_freq = pll_freq;
}

10
components/esp_phy/src/phy_init_esp32hxx.c
View File

@ -9,6 +9,10 @@
#include "esp_phy_init.h"
#include "esp_private/phy.h"
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
#include "esp_private/esp_modem_clock.h"
#endif
#define PHY_ENABLE_VERSION_PRINT 1
static DRAM_ATTR portMUX_TYPE s_phy_int_mux = portMUX_INITIALIZER_UNLOCKED;
@ -46,6 +50,9 @@ void esp_phy_enable(void)
{
_lock_acquire(&s_phy_access_lock);
if (s_phy_access_ref == 0) {
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_PHY_MODULE);
#endif
if (!s_phy_is_enabled) {
register_chipv7_phy(NULL, NULL, PHY_RF_CAL_FULL);
phy_version_print();
@ -73,6 +80,9 @@ void esp_phy_disable(void)
phy_track_pll_deinit();
phy_close_rf();
phy_xpd_tsens();
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_PHY_MODULE);
#endif
}
_lock_release(&s_phy_access_lock);

6
components/soc/esp32c6/include/soc/periph_defs.h
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@ -44,14 +44,16 @@ typedef enum {
PERIPH_SARADC_MODULE,
PERIPH_TEMPSENSOR_MODULE,
PERIPH_REGDMA_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */
PERIPH_WIFI_MODULE,
PERIPH_BT_MODULE,
PERIPH_IEEE802154_MODULE,
PERIPH_COEX_MODULE,
PERIPH_PHY_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
PERIPH_ANA_I2C_MASTER_MODULE,
PERIPH_MODULE_MAX
/* !!! Don't append soc modules here !!! */
} periph_module_t;
typedef enum {
@ -61,7 +63,7 @@ typedef enum {
} lp_periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_PHY_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_ANA_I2C_MASTER_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))

6
components/soc/esp32h2/include/soc/periph_defs.h
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@ -44,17 +44,19 @@ typedef enum {
PERIPH_SARADC_MODULE,
PERIPH_TEMPSENSOR_MODULE,
PERIPH_REGDMA_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */
PERIPH_BT_MODULE,
PERIPH_IEEE802154_MODULE,
PERIPH_COEX_MODULE,
PERIPH_PHY_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
PERIPH_ANA_I2C_MASTER_MODULE,
PERIPH_MODULE_MAX
/* !!! Don't append soc modules here !!! */
} periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_PHY_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_ANA_I2C_MASTER_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))