Commit Graph

16 Commits

Author SHA1 Message Date
Alexey Gerenkov
002411b169 riscv: Use 'li' instead of 'la' for loading peripheral reg address 2022-12-06 21:54:50 +03:00
Omar Chebib
53c7dd4efc WDT: implement interrupt wdt and task wdt for ESP32-C2
ESP32-C2 has a single group timer, thus it will use it for the interrupt watchdog,
which is more critical than the task watchdog. The latter is implement in
software thanks to the `esp_timer`component.
2022-09-15 14:37:59 +08:00
Alexey Gerenkov
72822dfc8f riscv: Adds support for returning from exception handler 2022-02-24 08:55:40 +00:00
Alexey Gerenkov
54569fb001 riscv: Fixes GDB backtrace of interrupted threads
Save missed SP value on stack
2022-02-24 08:55:40 +00:00
Omar Chebib
220e52fca1 RISC-V: Fix vectors.S assembly file indentation and macro usage
The file is now more consistent as the macros have been fixed, more comments
have been added and the indentation is now using spaces only.
2021-11-15 17:17:24 +08:00
Omar Chebib
0f6f3c0ece RISC-V: fix usage of special register when interrupts are enabled 2021-10-25 16:31:34 +08:00
Martin Vychodil
69096ddce5 Security: ESP32C3 memory protection feature (IRAM0/DRAM0)
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)

Closes https://jira.espressif.com:8443/browse/IDF-2092
2021-01-27 08:44:03 +01:00
Li Shuai
355dd10257 light sleep: dfs support for esp32c3 2021-01-19 14:50:58 +08:00
morris
9e7d2c0065 esp32c3: format and clean up interrupt and os port code 2021-01-05 15:39:46 +08:00
Felipe Neves
f4781d3b1d freertos: riscv port now uses interrupt allocator and crosscore interrupt 2021-01-05 15:39:46 +08:00
Felipe Neves
810be86f21 freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port.
The riscv vectors.S in riscv component contains the trap vector, which is responsible to
defer interrupts and examine if a task context switch is needed, this change cleans up
this code by hiding all freertos details behind on two functions rtos_it_enter/exit and
their implementations are placed in freertos riscv port files.
2021-01-05 15:39:46 +08:00
Omar Chebib
c218f669ba panic on RISC-V: Take into account Merge Request comments 2020-12-31 15:46:17 +08:00
Omar Chebib
a90dcfba1a panic: Add support for SoC-level panic
Activate "invalid access to cache raises panic (PRO CPU)" CI unit
test in order to test SoC-level panics.
2020-12-31 15:46:17 +08:00
Omar Chebib
b6a450f824 panic: Add support for SoC-level panic
SoC level exceptions such as watchdog timer and cache errors are now supported.
Such exceptions now triggers a panic, giving more information about how
and when it happened.
2020-12-31 15:46:17 +08:00
Renz Bagaporo
4cc6b5571b esp_system: support riscv panic 2020-11-13 07:49:11 +11:00
Angus Gratton
fccab8f4ef riscv: Add new arch-level component
Changes come from internal branch commit a6723fc
2020-11-12 09:33:18 +11:00