Commit Graph

97 Commits

Author SHA1 Message Date
Cao Sen Miao
11188d2143 esp_flash:fix bug about clearing WLE automatically after actions 2020-11-12 16:44:29 +08:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
weitianhua
1de3b17192 Fix BT controller dead issue caused by clk overflow 2020-10-29 10:49:30 +08:00
morris
9de6cba434 ci: add more build test for esp32-s3 2020-10-27 17:22:17 +08:00
Ivan Grokhotkov
48f27cb5ab Merge branch 'feature/esp32_ulp_allow_8kb' into 'master'
esp32: allow up to 8 kB of ULP program size

Closes IDFGH-1772

See merge request espressif/esp-idf!10727
2020-10-20 04:08:57 +08:00
Michael (XIAO Xufeng)
647dea9395 soc: combine xxx_caps.h into one soc_caps.h
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
2020-10-17 16:10:15 +08:00
Marius Vikhammer
949fb8e63a SHA: add HAL layer and refactor driver
Add a LL and HAL layer for SHA.
2020-10-09 08:24:08 +00:00
Ivan Grokhotkov
ef10c2576f esp32: allow up to 8 kB of ULP program size
The remaining 4 kB had been reserved for storing RF calibration and
BT stack state since 4e092be6. However, these features never got
implemented. If we ever need to place RF related data into RTC slow
memory, we can do this by creating a variable with RTC_NOINIT_ATTR
instead.

Closes https://github.com/espressif/esp-idf/issues/3993
2020-10-05 11:41:39 +02:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00
chenjianqiang
f19cabb7e4 psram: support psram for esp32s3 2020-09-22 15:15:03 +08:00
morris
6225932201 bootloader_support: add esp32-s3 initial support 2020-09-22 15:15:03 +08:00
Jiang Jiang Jian
cfc4be0f06 Merge branch 'bugfix/confirmed_bugfix_from_baidu_proj' into 'master'
component_bt/bugfix: Confirmed bugfix from Baidu project

See merge request espressif/esp-idf!10450
2020-09-22 11:38:29 +08:00
Angus Gratton
033f49f974 Merge branch 'bugfix/cpp_header_rom_secure_boot' into 'master'
Secure Boot: Fixes the cpp macro in esp32 secure boot rom functions.

Closes IDFGH-3998

See merge request espressif/esp-idf!10528
2020-09-21 15:51:03 +08:00
Supreet Deshpande
0e940c80d4 Secure Boot: Fixes the cpp macro in esp32 secure boot rom functions.
Closes https://github.com/espressif/esp-idf/issues/5878
2020-09-20 22:50:44 +05:30
Michael (XIAO Xufeng)
fefdee1349 bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.

   This commit helps to clear WEL when flash configuration is done.

   **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.

2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.

   Status register bitmap of ISSI chip and GD chip:

| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0  | WIP  | WIP       |
| 1  | WEL  | WEL       |
| 2  | BP0  | BP0       |
| 3  | BP1  | BP1       |
| 4  | BP2  | BP2       |
| 5  | BP3  | BP3       |
| 6  | QE   | BP4       |
| 7  | SRWD | SRP0      |
| 8  |      | SRP1      |
| 9  |      | QE        |
| 10 |      | SUS2      |
| 11 |      | LB1       |
| 12 |      | LB2       |
| 13 |      | LB3       |
| 14 |      | CMP       |
| 15 |      | SUS1      |

   QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.

   However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.

   Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.

   This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).

3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.

   This commit skips the clearing of status register if there is no protection bits active.

Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-09-19 10:51:51 +08:00
weitianhua
c598b816ba Confirmed bugfix from Baidu project 2020-09-15 19:36:20 +08:00
Jakob Hasse
20c068ef3b cmock: added cmock as component
* changing dependencies from unity->cmock
* added component.mk and Makefile.projbuild
* ignore test dir in gen_esp_err_to_name.py
* added some brief introduction of CMock in IDF
2020-09-02 16:38:37 +08:00
Michael (XIAO Xufeng)
5425ef4ee4 hal: extract hal component from soc component 2020-09-01 13:25:32 +08:00
Renz Bagaporo
14902da344 esp32: move disabling rom log to esp_rom 2020-08-17 19:08:56 +08:00
Angus Gratton
a2dc60b254 Merge branch 'feature/secure_boot_esp32s2' into 'master'
Feature/secure boot esp32s2

See merge request espressif/esp-idf!8254
2020-07-28 16:39:34 +08:00
morris
2917651478 esp_rom: extract common ets apis into esp_rom_sys.h 2020-07-27 15:27:01 +08:00
Angus Gratton
a91bd4078f secure boot: Fixes for ESP32-S2 first boot logic 2020-07-27 00:01:10 +00:00
morris
ab0537c079 esp_rom: extract common MD5 hash apis into esp_rom_md5.h 2020-07-21 17:01:28 +08:00
Ivan Grokhotkov
8739282a1d Merge branch 'feature/size_info_artifacts_for_apps' into 'master'
CI: add size info for binaries

Closes IDF-1709

See merge request espressif/esp-idf!8962
2020-07-21 16:00:07 +08:00
Fu Hanxi
6885421976 CI: add size info for binaries 2020-07-21 16:00:05 +08:00
morris
345606e7f3 esp_rom: extract common uart apis into esp_rom_uart.h 2020-07-17 16:00:59 +08:00
morris
458b14a8ea esp_rom: extract common efuse apis into esp_rom_efuse.h 2020-07-15 10:40:50 +08:00
morris
a4d0033c03 esp_rom: extract common GPIO apis into esp_rom_gpio.h 2020-07-07 11:40:19 +08:00
Ivan Grokhotkov
4f8c42ca73 esp_rom: add patch to set USB device serial descriptor to MAC address 2020-06-24 15:50:51 +02:00
Ivan Grokhotkov
4901917ea3 esp_rom: add USB related headers from the ROM code 2020-06-24 15:50:51 +02:00
morris
a34409cffc esp_rom: extract common CRC apis into esp_rom_crc.h 2020-06-23 16:40:14 +08:00
wangcheng
7bad9b77cc components/bt:Fix instant reverse and add ble connect paramter check. 2020-06-18 11:21:46 +08:00
morris
0daff849a4 esp_rom: remove unsupported library on esp32s2
Closes https://github.com/espressif/esp-idf/issues/5434
2020-06-11 21:40:08 +08:00
morris
be91b7c52e esp_rom: add esp32s3 rom headers 2020-06-11 21:40:08 +08:00
morris
9cc0f33ed5 esp_rom: add esp32s3 rom symbols 2020-06-11 21:40:08 +08:00
morris
783779c870 esp_rom: move rom api test into esp_rom component 2020-06-03 13:16:13 +08:00
weitianhua
77cc105c72 Fix ld_acl schedule bug to parity shift 2020-05-18 06:51:51 +00:00
weitianhua
b20f254483 Free lmp tx buf in EM in the procedure of handling LMP_detach_Req when not received the last acknowledge from peer device and seperate them by ACL State 2020-05-18 06:51:51 +00:00
morris
5d0860f2e8 fix broken CONFIG_LEGACY_INCLUDE_COMMON_HEADERS 2020-04-20 14:01:09 +08:00
KonstantinKondrashov
9aeac7f6cb esp_rom: Fix esp32.rom.newlib-time.ld should includes all time ROM functions/data
- Added UT
Closes: https://github.com/espressif/esp-idf/issues/4925
2020-03-27 04:57:42 +00:00
baohongde
d2aa4a1e50 components/bt: Fix assert when create conntion cancel 2020-02-28 20:13:41 +08:00
Mahavir Jain
5f897fd33c Merge branch 'feat/secure_boot_v2_v41' into 'master'
feat/secure_boot_v2: Adding secure boot v2 support to ESP32-ECO3

Closes IDF-799

See merge request espressif/esp-idf!6778
2020-02-27 18:54:08 +08:00
Angus Gratton
d40c69375c bootloader: Add fault injection resistance to Secure Boot bootloader verification
Goal is that multiple faults would be required to bypass a boot-time signature check.

- Also strengthens some address range checks for safe app memory addresses
- Change pre-enable logic to also check the bootloader signature before enabling SBV2 on ESP32

Add some additional checks for invalid sections:

- Sections only partially in DRAM or IRAM are invalid
- If a section is in D/IRAM, allow the possibility only some is in D/IRAM
- Only pass sections that are entirely in the same type of RTC memory region
2020-02-27 14:37:19 +05:30
michael
7a3f21636f spi_flash: fix the reading issue using the ROM functions in the ROM 2020-02-26 11:12:09 +08:00
Supreet Deshpande
a9ccc5e5c8 feat/secure_boot_v2: Adding secure boot v2 support for ESP32-ECO3 2020-02-25 01:28:22 +05:30
baohongde
d11a86076f Fix bugs about role switch
Jitter in FHS
Jitter in first PULL
Receive EDR packet fail after role switch
2020-02-19 20:14:47 +08:00
Michael (XIAO Xufeng)
278634dcbd sdspi: support crc16_be for esp32s2 2020-02-12 15:15:46 +08:00
Jiang Jiang Jian
7f4309d0f1 Merge branch 'feature/esp32_5p0_code_optimize' into 'master'
controller flash code optimize

See merge request espressif/esp-idf!7409
2020-02-11 17:29:08 +08:00
Ivan Grokhotkov
e5cb972c3a Merge branch 'bugfix/fix_esp32s2_flash_rw' into 'master'
flash(esp32s2): fix setting address field in spi user mode.

See merge request espressif/esp-idf!7380
2020-02-09 18:05:22 +08:00
Wangjialin
aaf119e930 flash(esp32s2): fix setting address field in spi user mode. 2020-02-07 16:10:51 +01:00