This commit fixes a bug wherein the RTC I2C peripheral got stuck after
the main CPU performs a soft reset by using esp_restart(). This is
because the RTC domain config registers for the RTC I2C domain are not
cleared after the soft restart and hence need to be cleared manually
while initializing the RTC I2C peripheral again.
Closes https://github.com/espressif/esp-idf/issues/10468
The RTC I2C peripheral always expects a I2C slave sub register address
to be programmed. If it is not programmed then a sub register address
available in SENS_SAR_I2C_CTRL_REG[18:11] is used for I2C read/write.
This commit updates the documentation of the API
ulp_riscv_i2c_master_set_slave_reg_addr() to clarify the same.
This commit fixes an issue where in the ULP RISC-V I2C example causes
a spurious wakeup of the main CPU because of a Trap signal when the ULP
core does not meet the wakeup threshold values. This was due to the fact
that the RTC_CNTL_COCPU_DONE signal was being set before the
RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V
core to not reset properly on each cycle.
Closes https://github.com/espressif/esp-idf/issues/10301
This commit adds support for using the RTC I2C peripheral on the ULP
RISC-V core for esp32s2 and esp32s3. It also adds an example to demonstrate the
usage of the RTC I2C peripheral.
This commit also modifies the rtc_i2c register structure files to enable
the use of bitfields in the ULP RISC-V RTC I2C driver.
There are multiple changes in this commit:
1. Unify the RISC-V and ULP-FSM code paths in esp32ulp_mapgen.py.
It seems that these were originally introduced because `nm` output
for the RISC-V case contained symbol sizes, while for the ULP-FSM
no symbol sizes were reported. This makes sense, because the
ULP-FSM object files are produced from assembly source, symbol
sizes have to be added manually using the .size directive.
In the case of RISC-V, the object files are built from C sources
and the sizes are automatically added by the compiler.
Now 'posix' output format is used for both RISC-V and ULP-FSM.
2. Move BASE_ADDR out of esp32ulp_mapgen.py. This now has to be passed
from CMake, which should make it easier to modify if a new chip
with a different RTC RAM base address is added.
3. Add C++ guards to the generated header file.
4. Switch from optparse to argparse for similarity with other IDF
tools.
5. Add type annotations.
* "dummy loop to force pre-processed linker file generation" seems to
be unnecessary. It looks like the idea was copied from the
dependency of ULP-FSM preprocessed source files on the LD script.
* Can use add_dependencies instead of
set_target_properties(...LINK_DEPENDS...) which is more readable
* Use target_link_options instead of target_link_libraries, which is
supported starting from CMake 3.13. Unlike target_link_libraries,
it doesn't require manually quoting the pats.
the variable "IDF_TARGET" is only used under a if clause
"if(ULP_C0CPU_IS_RISCV)". while building a non-riscv target,
there will be a cmake warning:
CMake Warning:
Manually-specified variables were not used by the project:
IDF_TARGET
Due to poor accuracy the ESP32 ULP TSENS instructions is not recommend for use.
We keep the instruction itself to support users which are already using it,
but should remove it from examples and docs to avoid encouring any new usage of it.
This updates the minimal supported version of CMake to 3.16, which in turn enables us to use more CMake features and have a cleaner build system.
This is the version that provides most new features and also the one we use in our latest docker image for CI.
