esp-idf

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History

Ivan Grokhotkov 2916bf9b6c

ulp: esp32ulp_mapgen: remove the special case for RISC-V, cleanup

There are multiple changes in this commit:

1. Unify the RISC-V and ULP-FSM code paths in esp32ulp_mapgen.py.
   It seems that these were originally introduced because `nm` output
   for the RISC-V case contained symbol sizes, while for the ULP-FSM
   no symbol sizes were reported. This makes sense, because the
   ULP-FSM object files are produced from assembly source, symbol
   sizes have to be added manually using the .size directive.
   In the case of RISC-V, the object files are built from C sources
   and the sizes are automatically added by the compiler.

   Now 'posix' output format is used for both RISC-V and ULP-FSM.

2. Move BASE_ADDR out of esp32ulp_mapgen.py. This now has to be passed
   from CMake, which should make it easier to modify if a new chip
   with a different RTC RAM base address is added.

3. Add C++ guards to the generated header file.

4. Switch from optparse to argparse for similarity with other IDF
   tools.

5. Add type annotations.

2022-08-30 02:34:28 +02:00

cmake

ulp: esp32ulp_mapgen: remove the special case for RISC-V, cleanup

2022-08-30 02:34:28 +02:00

ulp-riscv: add support for using ADC as well as an example show-casing it.

2022-07-11 09:31:22 +08:00

test_apps

ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP.

2022-08-05 18:16:31 +08:00

ulp_common

rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in

2022-05-24 22:59:41 +08:00