freertos: replace the freertos regular malloc to the specific malloc from xtensa port for tcb and stack allocations
freertos: avoid the cpu1 to unwind pended ticks when xTaskResumeAll is called insed of an ISR
freertos: protected the xPortGetCoreID functions with missing critical sections
tests: re-eanble the ignored tests that was failling before race-condition fixes
freertos/port: update the port files and split into xtensa and riscv ports
freertos: separated cpu files from rest of the kernel sources
freertos/port_xtensa: separated private include files into a folder
freertos/tasks: added task create pinned to core function do not break current IDF API
freertos/tasks: mimiced task create pinned function into tasks.c to do not break the IDF API.
freertos: freertos component now compiling
freertos: freertos component now building
freertos: moved critical sections outside from FR kernel section to portable section
portmacro_xtensa: add void indentifier on functions that take no arguments
freertos: fix critical sections implementation to match with their function prototype
freertos: add cmake changes of freertos into make
freertos: remove portDONT_DISCARD attribute from switch context function, it was breaking the docs building.
freertos: fix conflicitng types of vApplicationSleep function
license: update the license of freertos
freertos: Doxygen comments refactored to render them correctly on docs
freertos: added new functions of freertos into the documentation
freertos: added message buffers and stream buffers to documentation
sysview: update freertos system view to the compatible with version 10
freertos: fixed event group documentation rendering
freertos: update static task structure to match the actual tcb size
freertos: removed backported test functions
freertos/smp: brought SMP code to FreeRTOS 10 port
freertos/portmacro: added missing crosscore interrupt for yielding tasks
freertos: replaced soft-critical sections with hard-critical sections used by SMP
freertos: placed muxes inside of kernel objects
freertos: replaced original FR critical sections with SMP enabled spinlocks critical sections
freertos: moved xtensa port files to a separated folder
freertos: added multiple instance of global variables required to SMP
freertos: added SMP modifications on specific tasks module functions
freertos: added TLS deletion function to task module
freertos/tls: initialize TLS deletion callback to avoid crashing when calling task delete
freertos: modified vTaskDelete to do not erase current task that runs on other core
freertos: reverted taskhandle and timerhandle as void* type
freertos: fixed de-referencing void pointer to get run time counter
freertos: fix system view trace enter macro arguments
freertos: Replaced soft critical sections with spinlocks on event_groups
freertos: fixed tick function to avoid calling tick hooks twice
freertos: Nofity give checking per CPU if schedule is suspended
freertos: added mpu release on TCB deletion
freertos: Added SMP changes when deleting a TCB on idle task
freertos/license: update freertos license in COPYRIGHT.rst
freertos: unicore configurations can use task create pinned to core, it will be always pinned to core 0
freertos/portmacro: added cpu_hal_get_core_id() function instead of inline assembly
freertos/xtensa: update xtensa specific files used in master branch
newlib/locks: revert the preemption checking in lock acquisition and release
ref_clock: fix initial state of ref_clock interrupt handler
freertos: added missing critical sections and yielding checkings
freertos: remove magic numbers in vTaskDelete
freertos: added missing critical section in prvIsQueueEmpty
correct generation.py script to be silent when file: function is not in the object list (just ignore placement)
correct linker.lf to place task functions into flash if CONFIG_FREERTOS_TASK_FUNCTIONS_INTO_FLASH is active otherwise into IRAM
update kconfig option to place functions into IRAM
update linker file after tests
fix spi_device_polling_end crash when xTaskGetTickCount() in flash
disable "yield from lower priority task, other CPU" test case when placing rtos functions into flash
upadate ut app config freertos_flash
combine spi_flash driver and freertos ut configs into one file
remove TEST_EXCLUDE_COMPONENTS
ci: fix ut job
remove functions that are called from ISR funcs
add port module functions to place into Flash
place snapshot funcs into Flash when ESP_PANIC_HANDLER_IRAM is not set
ci: add job with tags UT_T1_GPIO,ESP32_IDF
Commit 891eb3b0 was fixing an issue with PS and EPC1 not being
preserved after the window spill procedure. It did so by saving PS in
a2 and EPC1 in a4. However the a4 register may be a live register of
another window in the call stack, and if it is overwritten and then
spilled to the stack, then the corresponding register value will end
up being corrupted. In practice the problem would show up as an
IllegalInstruction exception, when trying to return from a function
when a0 value was 0x40020.
Fix by using a0 register instead of a4 as scratch. Also fix a comment
about xthal_save_extra_nw, as this function in fact doesn't clobber
a4 or a5 because XCHAL_NCP_NUM_ATMPS is defined as 1.
Closes https://github.com/espressif/esp-idf/issues/5758
* changing dependencies from unity->cmock
* added component.mk and Makefile.projbuild
* ignore test dir in gen_esp_err_to_name.py
* added some brief introduction of CMock in IDF
Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.
1. Clarify THREADPTR calculation in FreeRTOS code, explaining where
the constant 0x10 offset comes from.
2. On the ESP32-S2, .flash.rodata section had different default
alignment (8 bytes instead of 16), which resulted in different offset
of the TLS sections. Unfortunately I haven’t found a way to query
section alignment from C code, or to use a constant value to define
section alignment in the linker script. The linker scripts are
modified to force a fixed 16 byte alignment for .flash.rodata on the
ESP32 and ESP32-S2beta. Note that the base address of .flash.rodata
was already 16 byte aligned, so this has not changed the actual
memory layout of the application.
Full explanation of the calculation below.
Assume we have the TLS template section base address
(tls_section_vma), the address of a TLS variable in the template
(address), and the final relocation value (offset). The linker
calculates:
offset = address - tls_section_vma + align_up(TCB_SIZE, alignment).
At run time, the TLS section gets copied from _thread_local_start
(in .rodata) to task_thread_local_start. Let’s assume that an address
of a variable in the runtime TLS section is runtime_address.
Access to this address will happen by calculating THREADPTR + offset.
So, by a series of substitutions:
THREADPTR + offset = runtime_address THREADPTR = runtime_address - offset
THREADPTR = runtime_address - (address - tls_section_vma + align_up(TCB_SIZE, alignment)) THREADPTR = (runtime_address - address) + tls_section_vma - align_up(TCB_SIZE, alignment)
The difference between runtime_address and address is same as the
difference between task_thread_local_start and _thread_local_start.
And tls_section_vma is the address of .rodata section, i.e.
_rodata_start. So we arrive to
THREADPTR = task_thread_local_start - _thread_local_start + _rodata_start - align_up(TCB_SIZE, alignment).
The idea with TCB_SIZE being added to the THREADPTR when computing
the relocation was to let the OS save TCB pointer in the TREADPTR
register. The location of the run-time TLS section was assumed to be
immediately after the TCB, aligned to whatever the section alignment
was. However in our case the problem is that the run-time TLS section
is stored not next to the TCB, but at the top of the stack. Plus,
even if it was stored next to the TCB, the size of a FreeRTOS TCB is
not equal to 8 bytes (TCB_SIZE hardcoded in the linker). So we have
to calculate THREADPTR in a slightly obscure way, to compensate for
these differences.
Closes IDF-1239
components/freertos: cleaned up multicore option scheduler.
components/freertos: more cleanup and test optimization to present realistic results
components/freertos: remove unused macros of optimized task selection when multicore is used
freertos/Kconfig: fix trailing space on optimized scheduler option
freertos/tests: moved test context variables inside of test task.
The public variables used on scheduling time test now were packed into a structure allocated on test case task stack and passed to tasks as arguments saving RAM comsumption.
DISABLED_FOR_TARGETS macros are used
Partly revert "ci: disable unavailable tests for esp32s2beta"
This partly reverts commit 76a3a5fb48.
Partly revert "ci: disable UTs for esp32s2beta without runners"
This partly reverts commit eb158e9a22.
Partly revert "fix unit test and examples for s2beta"
This partly reverts commit 9baa7826be.
Partly revert "efuse: Add support for esp32s2beta"
This partly reverts commit db84ba868c.
1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
