Commit Graph

210 Commits

Author SHA1 Message Date
Jiang Jiang Jian
0cf0757224 Merge branch 'bugfix/ulp_fsm_ci_v5.1' into 'release/v5.1'
ulp-system/ulp-fsm: clean up test cases (v5.1)

See merge request espressif/esp-idf!24070
2023-07-11 01:46:39 +08:00
Marius Vikhammer
ee91a42a33 ulp-system/ulp-fsm: clean up test cases 2023-07-04 02:59:15 +00:00
boarchuz
e707ad166d fix ULP FSM reg ops with addr > 0xFF 2023-06-15 14:00:45 +02:00
Sudeep Mohanty
267c5e37a2 lp-i2c: Added support for LP I2C peripheral to LP core
This commit adds support for the LP I2C peripheral driver to be used by
the LP core. An example is also added to demonstrate the usage of the LP
I2C peripheral from the LP core.
2023-05-19 07:33:01 +02:00
Jakob Hasse
a6cbf68991 compiler: replaced noreturn by __noreturn__ in header files
* noreturn may be replaced by third-party macros,
  rendering it ineffective

* Closes https://github.com/espressif/esp-idf/issues/11339
2023-05-18 12:49:40 +08:00
Marius Vikhammer
d17ab36645 Merge branch 'feature/c6_ulp_timer_v5.1' into 'release/v5.1'
ulp: lp timer support for lp core (v5.1)

See merge request espressif/esp-idf!23659
2023-05-16 09:19:56 +08:00
Marius Vikhammer
45fd8feba3 ulp: add support for using lp timer with lp core on C6 2023-05-10 09:39:24 +08:00
Sudeep Mohanty
08600cb1a3 ulp-riscv-i2c: Add ULP RISC-V I2C read/write timeout config option
The commit 88e4c06028 introduced a loop timeout for all ULP RISC-V I2C
transactions to avoid getting stuck in a forever loop. The loop timeout
was set to 500 msec by default. This commit improves on the concept by
making the loop timeout configurable via a Kconfig option in terms of
CPU ticks. If the timeout is set to -1 value then the transaction loops
will never timeout, therefore restoring the driver behavior before the
timeout was introduced.

The commit also updates the I2C Fast mode timings for esp32s2 which need
to be adjusted due to bus timing constraints.

Closes https://github.com/espressif/esp-idf/issues/11154
2023-05-09 15:07:50 +02:00
Marius Vikhammer
94d6614c88 Merge branch 'ci/fix_overwrite_pytest_configs_v5.1' into 'release/v5.1'
ci: fixed test apps overriding pytest configs (v5.1)

See merge request espressif/esp-idf!23495
2023-05-06 17:40:58 +08:00
Marius Vikhammer
3724bf6256 ci: fixed test apps overriding pytest configs 2023-04-27 14:29:06 +08:00
Marius Vikhammer
0bac174058 ulp: added sleep support for lp core
Added support for running LP core while hp core sleeps, as well
as waking up the hp core.
2023-04-27 09:51:41 +08:00
Sudeep Mohanty
88e4c06028 ulp-riscv-i2c: Updated ULP RISC-V I2C driver to abort when met with errors
The current ULP RISC-V RTC I2C driver got stuck in an infinite loop if
there is a I2C transaction error. This commit amends the driver flow to
abort the read/write operation if met with errors. It also adds a loop
timeout to avoid getting stuck in an infinite loop.The commit also
updates the default bus timing parameters for RTC I2C to be faster.
This commit also adds documentation help to guide users when they meet
with issues while working with the RTC I2C driver on the ULP RISC-V coprocessor.
2023-03-29 13:25:46 +02:00
Marius Vikhammer
b7fcf1c139 ulp-fsm: fixed potential sleep tests failures
If the ULP sent the wake-up signal before the main CPU went to sleep,
then the test case would get stuck in sleep.

Increased delay before sending the wake-up signal.
2023-03-22 11:39:33 +08:00
Zim Kalinowski
5016eb6269 ulp: fix and re-enable no-format warnings 2023-03-12 21:47:24 +01:00
Marius Vikhammer
284dabf17f ulp: added basic support for building and running a binary in the lp core 2023-03-09 10:12:23 +08:00
Sudeep Mohanty
a67d15fdea ulp: Added APIs to handle ULP signal ISRs for the main CPU
This commit introduces APIs to handle ULP signal ISRs when the main core
is not in sleepmode.

Closes https://github.com/espressif/esp-idf/issues/10737
2023-02-24 07:25:39 +00:00
Alexey Lapshin
61a7342acd tools: add riscv zicsr/zifencei because they were separated from i
https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4
2023-02-22 05:33:03 +00:00
Alexey Lapshin
5389ac4e04 tools: cmake: ignore linker RWX segment warnings 2023-02-22 05:33:03 +00:00
Sudeep Mohanty
522a216385 Merge branch 'feature/ulp_elf_output' into 'master'
ulp: Updated ULP CMakeLists.txt to output binary with .elf extension

Closes IDF-3060

See merge request espressif/esp-idf!22414
2023-02-20 15:08:35 +08:00
Sudeep Mohanty
8f93e4d0d5 ulp: Updated ULP CMakeLists.txt to output binary with .elf extension
This commit updates the ULP CMakeLists.txt to output the ULP binary with
a .elf extension. Currently the output file does not use any extension.
2023-02-17 10:44:24 +01:00
Omar Chebib
5e5343d429 TWDT: Use the new TWDT Kconfig options in the examples and tests 2023-02-17 11:22:25 +08:00
Sudeep Mohanty
3cc399f399 ulp-riscv: Added API ulp_riscv_reset to reset the ULP core
This commit adds a new API ulp_reisv_reset() to enable reseting of the
ULP core from the main core. This is particularly necessary in case the
ULP crashes due to any reason. Earlier the only way to recover the ULP
was to do a power reset. This commit also adds new test cases which
exercise this scenario.
2023-02-08 07:52:34 +00:00
Marius Vikhammer
8aaecb9b28 ulp-riscv: add more wakeup test cases 2023-01-17 16:41:48 +08:00
Sudeep Mohanty
28ccb3b414 Merge branch 'bugfix/rtc_i2c_stuck_after_esp_restart' into 'master'
ulp risc-v rtc i2c: Fix a bug where RTC I2C failed to initialize after esp_restart()

Closes IDFGH-9065

See merge request espressif/esp-idf!21862
2023-01-05 15:59:08 +08:00
Sudeep Mohanty
2df00a4b17 Merge branch 'docs/ulp_riscv_i2c_sub_reg_addr' into 'master'
ulp-riscv-i2c: Updated API documentation about sub register address usage

Closes IDFGH-9023

See merge request espressif/esp-idf!21838
2023-01-05 15:58:29 +08:00
Sudeep Mohanty
4a410391cc ulp risc-v rtc i2c: Fix a bug where RTC I2C failed to initialize after esp_restart()
This commit fixes a bug wherein the RTC I2C peripheral got stuck after
the main CPU performs a soft reset by using esp_restart(). This is
because the RTC domain config registers for the RTC I2C domain are not
cleared after the soft restart and hence need to be cleared manually
while initializing the RTC I2C peripheral again.

Closes https://github.com/espressif/esp-idf/issues/10468
2023-01-02 15:44:03 +01:00
Sudeep Mohanty
07a506bb02 ulp-riscv-i2c: Updated API documentation about sub register address usage
The RTC I2C peripheral always expects a I2C slave sub register address
to be programmed. If it is not programmed then a sub register address
available in SENS_SAR_I2C_CTRL_REG[18:11] is used for I2C read/write.
This commit updates the documentation of the API
ulp_riscv_i2c_master_set_slave_reg_addr() to clarify the same.
2022-12-29 09:58:24 +01:00
Sudeep Mohanty
099f648686 ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2
This commit fixes an issue where in the ULP RISC-V I2C example causes
a spurious wakeup of the main CPU because of a Trap signal when the ULP
core does not meet the wakeup threshold values. This was due to the fact
that the RTC_CNTL_COCPU_DONE signal was being set before the
RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V
core to not reset properly on each cycle.

Closes https://github.com/espressif/esp-idf/issues/10301
2022-12-27 07:44:26 +00:00
KonstantinKondrashov
9fd8f3786a all: Replaces memset/memcpy with hal_mem.. funcs where were used -Wstringop-overread, -Wstringop-overflow, -Warray-bounds
hal: Adds hal_memcpy and hal_memset
2022-11-30 19:22:41 +08:00
Marius Vikhammer
4a56758547 Merge branch 'bugfix/s3_ulp_riscv_cocpu_trap' into 'master'
ulp-riscv: always force COCPU clock on S3

Closes FCS-983

See merge request espressif/esp-idf!20632
2022-10-25 13:50:36 +08:00
Marius Vikhammer
7b5bdcf077 ulp-riscv: always force COCPU clock on S3
The coprocessor cpu trap signal doesnt have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU
2022-10-18 03:06:05 +00:00
Marius Vikhammer
23b5e54974 CI: add common debug helper sdkconfig that can be used in test apps 2022-10-12 11:47:04 +08:00
Sudeep Mohanty
93153bdfe1 ulp: add all 'ignore' tests to pytest framework
This commit adds a way to run all 'ignore' tests for ulp using the
pytest framework.
2022-10-06 12:58:11 +02:00
Alexey Lapshin
e6f7b1a3a0 tools: cmake: check tool supported version with idf_tools.py 2022-10-03 19:01:32 +04:00
Marius Vikhammer
cb48a7b9f9 Merge branch 'feature/ulp_fsm_adc_s3' into 'master'
ulp-fsm: Update ulp-fsm ADC example with S3 support

Closes IDFGH-6299

See merge request espressif/esp-idf!19924
2022-09-19 14:08:33 +08:00
Alexey Lapshin
a9bd454529 tools: update esp32ulp-elf to v2.35_20220830
Closes https://github.com/espressif/esp-idf/issues/6432
Closes https://github.com/espressif/binutils-esp32ulp/issues/23
2022-09-13 12:55:48 +04:00
Marius Vikhammer
77ba84eeb7 ulp-fsm: Update ulp-fsm ADC example with S3 support
Closes https://github.com/espressif/esp-idf/issues/7963
2022-09-07 16:48:06 +08:00
wuzhenghui
c5d8e94898 freertos, ulp: Fix header inclusion to be compatible with new esp32c6 target 2022-09-06 09:13:20 +00:00
Sudeep Mohanty
4fde033a5f ulp: Added support for RTC I2C driver for ULP RISC-V on esp32s2 and esp32s3
This commit adds support for using the RTC I2C peripheral on the ULP
RISC-V core for esp32s2 and esp32s3. It also adds an example to demonstrate the
usage of the RTC I2C peripheral.

This commit also modifies the rtc_i2c register structure files to enable
the use of bitfields in the ULP RISC-V RTC I2C driver.
2022-09-05 10:21:43 +02:00
Song Ruo Jing
06b517efcb ci: Modify build-test-rules.yml enable' to disable` to exclude preview targets 2022-09-01 12:38:00 +08:00
Ivan Grokhotkov
9aecfe2b9d
ulp: fix typo in peripherals ld file names 2022-08-30 02:34:28 +02:00
Ivan Grokhotkov
2916bf9b6c
ulp: esp32ulp_mapgen: remove the special case for RISC-V, cleanup
There are multiple changes in this commit:

1. Unify the RISC-V and ULP-FSM code paths in esp32ulp_mapgen.py.
   It seems that these were originally introduced because `nm` output
   for the RISC-V case contained symbol sizes, while for the ULP-FSM
   no symbol sizes were reported. This makes sense, because the
   ULP-FSM object files are produced from assembly source, symbol
   sizes have to be added manually using the .size directive.
   In the case of RISC-V, the object files are built from C sources
   and the sizes are automatically added by the compiler.

   Now 'posix' output format is used for both RISC-V and ULP-FSM.

2. Move BASE_ADDR out of esp32ulp_mapgen.py. This now has to be passed
   from CMake, which should make it easier to modify if a new chip
   with a different RTC RAM base address is added.

3. Add C++ guards to the generated header file.

4. Switch from optparse to argparse for similarity with other IDF
   tools.

5. Add type annotations.
2022-08-30 02:34:28 +02:00
Ivan Grokhotkov
4b03e233d0
ulp: cmake: simplify the dependency on the generated LD script
* "dummy loop to force pre-processed linker file generation" seems to
  be unnecessary. It looks like the idea was copied from the
  dependency of ULP-FSM preprocessed source files on the LD script.
* Can use add_dependencies instead of
  set_target_properties(...LINK_DEPENDS...) which is more readable
* Use target_link_options instead of target_link_libraries, which is
  supported starting from CMake 3.13. Unlike target_link_libraries,
  it doesn't require manually quoting the pats.
2022-08-30 02:34:28 +02:00
Ivan Grokhotkov
67bd7a300a
ulp: cmake: add the target early, use target_* commands everywhere
Instead of collecting options in various variables, use CMake
commands like target_sources and target_link_options.
2022-08-30 02:34:28 +02:00
Ivan Grokhotkov
1a73374f82
ulp: move the expected ULP-FSM toolchain version from .mk to CMake
toolchain_ulp_version.mk is a remnant of the time when we had two
build systems, and CMake had to read the expected version from a
makefile.
2022-08-30 02:34:28 +02:00
Marius Vikhammer
ffed60cc93 ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP. 2022-08-05 18:16:31 +08:00
Marius Vikhammer
75cdc683ff ulp: fix -Wformat errors in ULP tests 2022-08-04 12:19:28 +08:00
Marius Vikhammer
bc08de5f46 Merge branch 'feature/ulp_test_app' into 'master'
ulp: migrate tests to pytest embedded

Closes IDF-5605

See merge request espressif/esp-idf!19342
2022-08-04 09:12:56 +08:00
Ivan Grokhotkov
401c10ecfb build system: re-add -Wno-format as private flag for some components 2022-08-03 16:42:47 +04:00
Marius Vikhammer
035924a8f1 ulp: migrate tests to pytest embedded 2022-08-03 09:36:17 +08:00