156 Commits

Author	SHA1	Message	Date
jack	24011ddd05	header files: modify rom code and soc header files ... 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions	2016-09-12 17:47:49 +08:00
Wu Jian Gang	ef36779bd3	ld: add ld for bt/trace, choose different ld by menuconfig	2016-08-25 11:34:21 +08:00
Wu Jian Gang	3e8bb67e75	ld: fix ld to use ram as much as possible, rearrange heap_alloc area	2016-08-25 11:07:53 +08:00
Wu Jian Gang	c3102e8fb2	ld: seperate/rename eagle.xxx.ld to esp32.xxx.ld	2016-08-25 11:07:53 +08:00
Ivan Grokhotkov	9e57466c96	components/esp32: fix DRAM_ATTR attribute ... This change places contents of .dram1 section into .dram0.data. Also removes .iram1pro/.iram1app/.dram1pro/.dram1app which weren't used anywhere.	2016-08-24 17:20:00 +08:00
Ivan Grokhotkov	bd6ea4393c	Initial public version	2016-08-17 23:08:22 +08:00