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ld: add ld for bt/trace, choose different ld by menuconfig
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3e8bb67e75
commit
ef36779bd3
@ -6,16 +6,32 @@
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# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
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# please read the esp-idf build system document if you need to do this.
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#
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-include $(PROJECT_PATH)/build/include/config/auto.conf
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LIBS := crypto core net80211 phy rtc pp wpa wps
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ifeq ($(CONFIG_MEMMAP_BT),y)
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ifeq ($(CONFIG_MEMMAP_TRACEMEM),y)
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LINKER_SCRIPTS = -T esp32.bt.trace.ld
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else
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LINKER_SCRIPTS = -T esp32.bt.ld
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endif
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else
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ifeq ($(CONFIG_MEMMAP_TRACEMEM),y)
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LINKER_SCRIPTS = -T esp32.trace.ld
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else
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LINKER_SCRIPTS = -T esp32.ld
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endif
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endif
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LINKER_SCRIPTS += -T esp32.common.ld -T esp32.rom.ld
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COMPONENT_ADD_LDFLAGS := -lesp32 \
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$(abspath libhal.a) \
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-L$(abspath lib) \
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$(addprefix -l,$(LIBS)) \
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-L $(abspath ld) \
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-T eagle.fpga32.v7.ld \
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-T eagle.fpga32.rom.addr.v7.ld
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$(LINKER_SCRIPTS)
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include $(IDF_PATH)/make/component.mk
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14
components/esp32/ld/esp32.bt.ld
Normal file
14
components/esp32/ld/esp32.bt.ld
Normal file
@ -0,0 +1,14 @@
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/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
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/* The load addresses are defined later using the AT statements. */
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
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dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x40000 /* Shared RAM, minus rom bss/data/stack.*/
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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}
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_heap_end = 0x40000000;
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14
components/esp32/ld/esp32.bt.trace.ld
Normal file
14
components/esp32/ld/esp32.bt.trace.ld
Normal file
@ -0,0 +1,14 @@
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/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
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/* The load addresses are defined later using the AT statements. */
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
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dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x38000 /* Shared RAM, minus rom bss/data/stack.*/
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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}
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_heap_end = 0x3FFF8000;
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14
components/esp32/ld/esp32.trace.ld
Normal file
14
components/esp32/ld/esp32.trace.ld
Normal file
@ -0,0 +1,14 @@
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/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
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/* The load addresses are defined later using the AT statements. */
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
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dram0_0_seg (RW) : org = 0x3FFB0000, len = 0x48000 /* Shared RAM, minus rom bss/data/stack.*/
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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}
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_heap_end = 0x3FFF8000;
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