Sudeep Mohanty
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2ed15d8b1e
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ulp: Added ULP RISC-V support for esp32s3
This commit adds support for ULP RISC-V for esp32s3.
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
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2022-01-18 10:58:00 +05:30 |
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Marius Vikhammer
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386739595f
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RISCV-ULP: Add DS18B20 1wire RISCV-ULP example
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2021-06-25 11:26:39 +08:00 |
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Angus Gratton
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3ee4370578
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esp32s2 riscv ulp: Ensure reset vector is always at offset 0x0
Previous linker script relied on nothing else using the .text section
As reported at https://esp32.com/viewtopic.php?f=2&t=20734&p=75997
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2021-05-06 09:25:32 +10:00 |
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Angus Gratton
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66fb5a29bb
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Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.
(Line endings, blank lines at end of file, trailing whitespace)
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2020-11-11 07:36:35 +00:00 |
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Felipe Neves
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b6dba84323
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ulp: added support to building code for riscv ULP coprocessor
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2020-07-15 15:28:49 -03:00 |
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