Commit Graph

86 Commits

Author SHA1 Message Date
Omar Chebib
55acc5e5e7 feat(riscv): add support for PIE coprocessor and HWLP feature
FreeRTOS tasks may now freely use the PIE coprocessor and HWLP feature.
Just like the FPU, usiing these coprocessors result in the task being pinned
to the core it is currently running on.
2024-05-20 10:47:58 +08:00
Konstantin Kondrashov
40684a0e1c Merge branch 'feature/freertos_runtime_counter_support' into 'master'
feat(freertos): Runtime Counter support

Closes IDFGH-12057

See merge request espressif/esp-idf!30150
2024-04-18 18:01:34 +08:00
Konstantin Kondrashov
66e6a48efd feat(freertos): Runtime Counter support
Closes https://github.com/espressif/esp-idf/issues/13120
2024-04-18 10:26:38 +03:00
Jiang Jiang Jian
5f19a8797a Merge branch 'contrib/github_pr_13022' into 'master'
fix(freertos): Fix broken portable macro portTRY_ENTER_CRITICAL_SAFE()

Closes IDFGH-11943

See merge request espressif/esp-idf!30030
2024-04-17 10:41:10 +08:00
Omar Chebib
f6e935e013 fix(esp32c5): add CLIC interrupt controller support for the ESP32-C5 2024-04-16 10:38:14 +08:00
Andy Lin
4f6deb9f61 fix(freertos): Fix broken portable macro portTRY_ENTER_CRITICAL_SAFE()
This commit fixes a bug where the portTRY_ENTER_CRITICAL_SAFE() for the
Xtensa and RISC-V FreeRTOS ports were broken as it did not correctly use
the timeout parameter.

Merges: https://github.com/espressif/esp-idf/pull/13022
2024-04-03 14:35:31 +02:00
wanlei
a611e91b2f feat(esp32c61): new chip add system and esp_timer support 2024-03-21 11:31:15 +08:00
Alexey Lapshin
40be44f827 feat(system): refactor linker scripts
- move .tbss to NOLOAD section
- remove xtensa-specific entities from riscv scripts
- explicit eh_frame terminator instead of "align magic"
- 80 characters line length limit
- refactor comments
- discard .rela sections (the rela data will go to relates sections)
2024-03-19 13:27:11 +04:00
laokaiyao
24d6dcb829 feat(esp32c5mp): add system related components 2024-03-18 17:34:56 +08:00
Sudeep Mohanty
e4f167df25 Merge branch 'fix/freertos_optimize_critical_sections' into 'master'
fix(riscv): Updated RISC-V functions to set interrupt threshold for CLIC targets

Closes IDFCI-2033, IDFCI-2034, IDF-8090, and IDF-8117

See merge request espressif/esp-idf!29055
2024-03-01 17:51:14 +08:00
Alexey Lapshin
824c8e0593 feat(esp_system): allow .bss to spill over into L2MEM above 0x4ff40000
This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:

- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
  SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data

If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):

  .dram0.bss (NOLOAD) :
  {
    arrays[dram0_bss]
    mapping[dram0_bss]
  } > sram_low

  .dram1.bss (NOLOAD) :
  {
    /* do not place here arrays[dram0_bss] because it may be splited
     * between segments */
    mapping[dram0_bss]
  } > sram_high
2024-02-28 19:41:25 +04:00
Sudeep Mohanty
459ff8348f fix(riscv): Added RISC-V functions to set interrupt threshold for CLIC targets
This commit added the RISC-V utility functions to set the interrupt
threshold for CLIC targets by using direct register value writes.
This makes the functions more efficient during run-time.
This is done to improve the critical section enter and exit performance on esp32p4.
2024-02-28 08:51:37 +01:00
Erhan Kurubas
029a0582e1 feat(coredump): improve the probability of accessing healthy TCBs 2024-01-22 00:18:28 +08:00
Omar Chebib
cdde05335e Merge branch 'refactor/riscv_interrupt' into 'master'
refactor(riscv): Refactor crosscore interrupts and core interrupt code

Closes IDF-5720, DOC-5177, and IDF-7899

See merge request espressif/esp-idf!27845
2024-01-19 10:51:04 +08:00
Omar Chebib
102d5bbf72 refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
Omar Chebib
5cdf145f55 refactor(riscv): refactor crosscore interrupt 2024-01-18 16:27:36 +08:00
Omar Chebib
c7e63078b7 fix(riscv): adjust TCBs lowest stack address when the FPU is used 2024-01-18 13:06:29 +08:00
Sudeep Mohanty
d4ca7c246e fix(freertos): Fixed incorrect int level restoration on esp32p4
This commit fixes a bug where in the portENABLE_INTERRUPTS() macro
incorrectly restored the interrupt level to 1 (non-CLIC controller).
2024-01-05 11:00:56 +01:00
Darian Leung
439c7c4261 change(freertos/idf): Remove xCoreID TCB member for single-core
This commit does the following:

- removes the xCoreID member from the TCB when building for single-core
- xCoreID is no longer hard set to 0 when calling "PinnedToCore" task creation
functions in single-core
- Tidy up or add missing xCoreID asserts for functions that take xCoreID as an
argument:
    - Functions that set/query a variable of a particular core will call
      taskVALID_CORE_ID() to ensure ) 0 <= xCoreID < configNUMBER_OF_CORES
    - Task creation functions that accept xCoreID also call taskVALID_CORE_ID()
      but also allow tskNO_AFFINITY.
- Fix TaskStatus_t
    - Remove xCoreID from TaskStatus_t if configTASKLIST_INCLUDE_COREID is not
      defined.
    - Set xCoreID to 0 when calling vTaskGetInfo() in single-core builds
2023-12-02 15:46:07 +08:00
Sudeep Mohanty
d507a86285 feat(freertos): Exposed Kconfig option for configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
This commit exposes the FreeRTOS List integrity check option
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES via menuconfig.
2023-11-09 14:54:13 +01:00
Omar Chebib
a8b1475fe7 feat(riscv): implement coprocessors save area and FPU support
This commit mainly targets the ESP32-P4. It adds supports for coprocessors on
RISC-V based targets. The coprocessor save area, describing the used coprocessors
is stored at the end of the stack of each task (highest address) whereas each
coprocessor save area is allocated at the beginning of the task (lowest address).
The context of each coprocessor is saved lazily, by the task that want to use it.
2023-10-23 11:10:28 +08:00
Darian Leung
82ad04e3ba change(freertos/idf): Update version number, licenses, and sbom to v10.5.1
Following the upgrade to FreeRTOS kernel v10.5.1, this commit updates the
version numbers, licenses, and SBOM files of FreeRTOS files to reflect v10.5.1.

Note:

- Updated licenses as v10.5.1 now uses SPDX format
- Removed CVE-2021-43997 as it was fixed post v10.4.5
2023-10-21 04:39:16 +08:00
Darian Leung
16ccb31d33 change(freertos/idf): Make v10.5.1 the default kernel
This commit makes v10.5.1 the default FreeRTOS kernel in ESP-IDF by removing
the CONFIG_FREERTOS_USE_KERNEL_10_5_1 option and v10.4.3 specific code
blocks.
2023-10-21 04:39:16 +08:00
Sudeep Mohanty
cf55ab899a fix(freertos): Fixed xPortCanYield to correctly determine ISR context on esp32p4
This commit fixes an issue where xPortCanYield() function may not be
able to detect an ISR context when HW interrupt nesting is active on
a CLIC interrupt controller such as on esp32p4.
2023-10-09 09:12:15 +02:00
Darian Leung
b09462eae8 feat(freertos): Add beta support for FreeRTOS v10.5.1 kernel
This commit adds beta support for the FreeRTOS v10.5.1 kernel which can be
enabled by enabling the CONFIG_FREERTOS_USE_KERNEL_10_5_1 option.

The following changes have been made:

- Updated freertos/CMakeLists.txt to build v10.5.1 kernel with v10.4.3. ports
- Updated existing Xtensa and RISC-V ports to work with V10.5.1
- Modifications to other ESP-IDF components to work with v10.5.1
- Added some ESP-IDF specific tracing changes to v10.5.1 kernel
- Make CONFIG_FREERTOS_USE_KERNEL_10_5_1 a public option

Note: The beta release is missing some minor fixes, performance improvements,
and features. Using this beta release for production is not recommended.

Closes https://github.com/espressif/esp-idf/issues/7137
2023-09-18 21:32:14 +08:00
KonstantinKondrashov
25c7a59e31 fix(freertos): Use INTERRUPT_CURRENT_CORE_INT_THRESH_REG for esp32p4 2023-09-07 15:25:35 +08:00
Sudeep Mohanty
62ee4135e0 Merge branch 'bugfix/freertos_incorrect_xPortCanYield' into 'master'
fix(freertos): Corrected xPortCanYield() for esp32p4

See merge request espressif/esp-idf!25679
2023-09-04 09:33:25 +08:00
Sudeep Mohanty
d9a3e3bb86 fix(freertos): Corrected xPortCanYield() for esp32p4
This commit updates the xPortCanYield() for esp32p4 by correcting the
return condition. Previously, the API would return true if an ISR of
priority 1 was received which is incorrect.
2023-08-31 17:45:17 +08:00
Omar Chebib
8ca191e4c1 fix(esp32p4): Fixed interrupt handling to use the CLIC controller 2023-08-31 12:16:08 +08:00
Darian
ede131ce73 Merge branch 'refactor/freertos_tslfcb_and_coproc_cleanup' into 'master'
refactor(freertos): Remove portCLEAN_UP_COPROC() and TLSP deletion callback kernel changes from IDF FreeRTOS

See merge request espressif/esp-idf!25481
2023-08-25 15:34:40 +08:00
Marius Vikhammer
e07023292a Merge branch 'feature/p4_spinlocks' into 'master'
esp32p4: support spinlocks

Closes IDF-7771

See merge request espressif/esp-idf!25036
2023-08-25 11:43:38 +08:00
Darian Leung
57eb41ce83 refactor(freertos): Call TLSP deletion callback from portCLEAN_UP_TCB()
Previously, TLSP deletion callbacks were...

- Stored in a seprate TCB member "pvThreadLocalStoragePointersDelCallback"
- Called separately via multipole prvDeleteTLS() insertions in tasks.c

This commit refactors how TLSP deletion callbacks are stored and called:

- TLSP deletion callbacks are now stored in "pvThreadLocalStoragePointers"
directly. configNUM_THREAD_LOCAL_STORAGE_POINTERS is doubled in size so that
the deletion callbacks are stored in the latter half of the array

- The callbacks are now called via "portCLEAN_UP_TCB()". As such, the
prvDeleteTLS() additions are no longer needed and the function can be removed

- Removed some legacy TLSP tests using the old method of storing the callback
pointers.

This commit reduces the source code diff between IDF FreeRTOS and upstream
vanilla FreeRTOS, in preparation for v10.5.1 upgrade.
2023-08-24 19:32:06 +08:00
Marius Vikhammer
0d9f9e6816 feat(core-systems): add support for spinlock/compare and set on esp32p4 2023-08-24 10:30:25 +08:00
Darian Leung
39cf3638ae change(freertos): Deprecate usage of vPortCleanUpTCB() by applications
Previously, if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP was enabled, users
would provide a definition for a vPortCleanUpTCB() hook function that is called
right before a task's memory is freed in prvDeleteTCB(). However,
vPortCleanUpTCB() will be reclaimed by ESP-IDF for internal use in v6.0.

This commit introduces the following changes...

Introduced a new CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK option:

- Provides the same pre-deletion hook functionality. But users now define
vTaskPreDeletionHook() instead.
- CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP still exists, but is marked as
deprecated. This is to maintain compatibility with existing applications
that already define vPortCleanUpTCB().
- Removed redundant --wl --wrap workaround with vPortCleanUpTCB()
- Added todo notes to remove support for user defined vPortCleanUpTCB()
completely in v6.0.
- Updated test cases to use new CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK option

Freed up portCLEAN_UP_TCB() to call a new internal vPortTCBPreDeleteHook():

- vPortTCBPreDeleteHook() now replaces the previous "wrapped" implementation
of vPortCleanUpTCB().
- vPortTCBPreDeleteHook() is an internal task pre-delete hook for IDF FreeRTOS
ports to inject some pre-deletion operations.
- Internal pre-delete hook now invokes user provided vTaskPreDeletionHook()
if enabled.
- Relocated vPortTCBPreDeleteHook() to correct section in port.c
2023-08-23 17:50:08 +08:00
Sudeep Mohanty
4e51c6b049 feat(freertos): Added changes for multi-core RISC-V port for FreeRTOS
This commit updates the FreeRTOS port layer for multi-core RISC-V targets.
2023-08-22 15:35:15 +08:00
Armando
fd096c012d change(vector.S): port hw stack guard change to p4 2023-07-25 05:59:10 +00:00
Armando
5986e63c47 change(riscv): added fence after CLIC_INT_THRESH_REG is set 2023-07-25 05:59:10 +00:00
Armando
48ee1ba36e feat(freertos): base support on p4 2023-07-25 05:59:10 +00:00
Alexey Lapshin
4df3ff619e feat(esp_system): implement hw stack guard for riscv chips
- add hardware stack guard based on assist-debug module
- enable hardware stack guard by default
- disable hardware stack guard for freertos ci.release test
- refactor rtos_int_enter/rtos_int_exit to change SP register inside them
- fix panic_reason.h header for RISC-V
- update docs to include information about the new feature
2023-07-01 16:27:40 +00:00
Darian Leung
6895e92fd2 freertos: Combine Amazon SMP FreeRTOS and IDF FreeRTOS config files
This commit merges the "FreeRTOSConfig_smp.h" file into the "FreeRTOSConfig.h".
The configurations for all FreeRTOS implementations are now stored in a single
file.
2023-03-22 16:32:29 +08:00
Darian Leung
05bda6595d freertos: Move FreeRTOSConfig_arch.h
This commit moves the FreeRTOSConfig_arc.h to the "esp_additions" directory
so that they can also be used for SMP FreeRTOS builds.
2023-03-22 16:32:29 +08:00
Darian Leung
e21ab0332b freertos(IDF): Refactor port heap functions
Vanilla FreeRTOS expects applications to use one of the heap implementations
provided by FreeRTOS (i.e., heap_x.c), where functions such as pvPortMalloc()
and vPortFree() are defined in the heap implementation.

However, ESP-IDF already provides its own heap implementation
(i.e., esp_heap_caps.h). Thus, the pvPortMallc()/vPortFree() functions were
previously overriden by macro to call esp_heap functions directly.

This commit refactors the FreeRTOS port's heap as such:

- Added a heap_idf.c that implements all of the heap related functions required
  by FreeRTOS source
- All dynamic memory allocated by FreeRTOS is from internal memory. Thus, the
  FreeRTOS heap is the internal memory subset of the ESP-IDF heap.
- Removed some old macros to reduce diff from upstream source code.
2023-03-06 16:00:29 +08:00
Alexey Lapshin
d1214aef8c freertos: riscv: fix vPortTaskWrapper for clang 2023-02-20 13:09:42 +08:00
Darian Leung
92bbf85350 freertos: Fix clang-tidy warning on pxPortInitialiseStack() 2022-12-23 15:29:17 +08:00
Darian Leung
09690906e7 freertos: Refactor OS startup functions
This commit refactors the OS startup functions as follows:

- Moved the OS/app startup functions listed below to "app_startup.c". Their
    implementations are now common to all ports (RISC-V and Xtensa) of all
    FreeRTOS implementations (IDF and Amazon SMP).
    - esp_startup_start_app()
    - esp_startup_start_app_other_cores()
- Removed esp_startup_start_app_common() as app startup functions are now
    already common to all ports.
- Added extra logs to "main_task" to help with user debugging

Note: Increased startup delay on "unity_task". The "unity_run_menu()" is non
blocking, thus if the main task or other startup tasks have not been freed
by the time "unity_run_menu()" is run, those tasks will be freed the next time
"unity_task" blocks. This could cause some tests to have a memory leak, thus
the "unity_task" startup delay has increased.
2022-12-08 01:57:30 +08:00
Alexey Gerenkov
47c2c13de5 build: Adds support for universal Clang toolchain 2022-11-23 13:25:16 +03:00
Omar Chebib
6fe563163c RISC-V: fix PC not saved when using backtrace 2022-11-18 15:07:38 +08:00
Omar Chebib
d580f6b076 RISC-V: Create a wrapper around FreeRTOS Tasks to detect the ones returning 2022-11-18 15:07:32 +08:00
Sudeep Mohanty
ac99c0ad6b Merge branch 'feature/freertos_remove_untested_fn_feature' into 'master'
freertos: Removed CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION kconfig option

Closes IDF-5298

See merge request espressif/esp-idf!21000
2022-11-16 10:28:42 +08:00
Omar Chebib
bcb8516744 FreeRTOS: Make the default stack alignment 16 for Xtensa 2022-11-11 19:31:20 +08:00