bootloader: export ets_update_cpu_frequency
MR !363 added linking librtc into bootloader. At the same time, MR !373 removed ets_update_cpu_frequency from ROM exports ld script, and replaced it with a dual CPU aware version. Combining these two MRs caused linker error in bootloader due to the unresolved `ets_update_cpu_frequency`.
One option to fix this is to move the definition of ets_update_cpu_frequency into bootloader_support component. This does however look a bit odd because this function is not something that is specifically needed for bootloader support.
Another option is to export the ROM version of ets_update_cpu_frequency for the bootloader only. This means that when bootloader changes CPU frequency, it only updates the tick period variable for PRO CPU. This isn't an issue though, because app startup code still calls the dual CPU aware version of ets_update_cpu_frequency early on, before any non-trivial code can run on the APP cpu.
This MR uses the second approach. Looking forward, we may move this definition of ets_update_cpu_frequency into the rtc_clk component, which will be used both by the bootloader and the app, and placing ets_update_cpu_frequency there would be logical.
See merge request !384
SDMMC peripheral driver, SD protocol driver, FATFS library, VFS integration
This MR contains:
- SDMMC host peripheral driver
- SD protocol driver in sdmmc component (can be extended to support MMC/eMMC and SPI based hosts)
- ChaN's FATFS library v0.12b
- VFS integration
- FAT access via VFS is thread-safe (unless same file is read/written/unlinked/renamed from different tasks)
- Support for POSIX directory-related functions in VFS (and in vfs_fatfs.c)
- unit test for the above
- Example
- API documentation
Will be done in other MRs:
- Support for spi_flash IO driver for FatFs
- SPI host driver and support for SPI mode commands in sdmmc component
- MMC/eMMC support in sdmmc component
- Support for slightly higher 53/26.6MHz clocks (currently I'm using 20MHz for DS and 40MHz for HS, instead of 25MHz/50MHz per standard), and arbitrary low clocks (e.g. 4MHz).
See merge request !353
C++ support
This change adds necessary support for compiling C++ programs:
- linking against libstdc++
- implementation of static initialization guards using FreeRTOS primitives: since we don't have condition variables at our disposal, and we don't want to allocate a synchronization primitive for every guard variable generated by the compiler, we imitate condition variables using a combination of a mutex, counting semaphore, and a counter (based on [Microsoft Research paper](https://www.microsoft.com/en-us/research/wp-content/uploads/2004/12/ImplementingCVs.pdf), albeit because we don't need *arbitrary* code to use these CVs, implementation gets simpler).
Note that libstdc++ also contains an implementation of `__cxa_guard_{acquire,release,abort}` functions. These implementations come from an `#ifndef GXX_THREADS` branch, i.e. are not aware of multthreading. There are three ways of replacing these libstdc++ functions with our implementation:
1. Move our code into gcc. Pros: cleanest solution. Cons: Such changes are unlikely to be merged by any upstream, so we end up maintaining our own forks of {gcc,crosstool-ng}.
2. Use library as it is built by crosstool, use `ar` to delete one object file (`guards.o`), add this library to ESP-IDF. Pros: easy to implement. Cons: libstdc++ is a 15MB binary 😯
3. Keep using libstdc++ from crosstool, force our implementation to be linked using a `-u` linker flag. Pros: no impact on repo size, easy to implement. Cons: somewhat less clean than 1 (and about as hacky as 2).
For the reasons mentioned, option (3) looks like the best tradeoff.
Ref. TW6702
See merge request !364
Enable bootloader entropy source for RNG
Enables an entropy source when bootloader starts up, which both seeds the RNG for use before WiFi/BT stack is enabled and provides an adequate RNG for secure boot & flash encryption key generation.
A prerequisite was enabling 80MHz operation, so the CPU is now set to 80MHz as soon as second stage bootloader starts running.
See merge request !363
add menuconfig option to enable SO_RCVBUF
This option is required by Arduino and enables netconn connection to be queried for amount of data available in the rx buffer.
See merge request !372
esp32: ets_update_cpu_frequency should set tick scale for both CPUs
ets_update_cpu_frequency ROM function updates g_ticks_per_us, which is has two copies, one for each CPU.
The APP CPU copy of g_ticks_per_us never got updated, resulting in shorter delays produced by ets_delay_us on the APP CPU.
This MR replaces ROM ets_update_cpu_frequency with a copy in IRAM which updates scaling factors on both of the CPUs.
So now we get expected delays (in microseconds):
```
ets_delay_us core=0 expected=50000 actual=50014
ets_delay_us core=1 expected=50000 actual=50015
vTaskDelay core=0 expected=50000 actual=49428
vTaskDelay core=1 expected=50000 actual=50000
```
Reported on the forum: http://esp32.com/viewtopic.php?f=2&t=713#p3722
See merge request !373
SPI master driver
This merge requests adds an SPI Master driver. This driver is (of course) multithread capable, has device abstraction, has command queueing, DMA support and all other sorts of nice things you'd expect from a SPI driver.
See merge request !332
modify bootloader dram start address, swap app bss and data segments
Modify bootloader dram_seg from address 0x3ffc0000 to 0x3fff0000, len from 0x20000 to 0x10000.
Also put app .data before .bss, to reduce the chance .data collides with ROM bootloader stack.
See merge request !375
This change reduces chances that a large .bss segment will push .data all the way into
0x3ffe1320 — 0x3ffe5320 range where the bootloader stack is, creating a problem when
bootloader will be loading application into memory.
With this change, .data would need to be at least 200k big to cause problems.
Modify bootloader dram_seg from address 0x3ffc0000 to 0x3fff0000, len from
0x20000 to 0x10000. Please be notified that this is just a workaround for
fixing app data overwrite bootloader data issue!
1. add fading functions.
2. clear up ledc.c and ledc.h
3. update api doc.
4. add ledc example
5. edit ledc.rst and add readme for example code.
6. add s_ prefix for static global values.
7. add mutex for fade functions
8. minor changes according to the comments.
1. add method of any version supporting at OpenSSL and add API in header file
2. change OpenSSL server context method to be method of any version
Fixes http://esp32.com/viewtopic.php?f=14&t=696.
1. Update wifi lib which contains ampdu and other optimizations
2. Add throughput code debug code
3. Other misc modification about throughput optimization
2. update example comments and other minor changes
3. rename API: i2c_cmd_link_create/i2c_cmd_link_delete (+4 squashed commits)
Squashed commits:
[2e0ac3e] 1. coding style: add one space after condition key words.
2. modify i2c.h, use gpio_num_t instead of int, improve comments of return values
3. add i2c index in index.rst
4. add readme for i2c example
[4991d92] update i2c.doc
[88b672e] driver: i2c
1. add mux and spin lock to run in a thread-safe way.
2. modify example code
[4eb15fe] driver: i2c code
1. add i2c master code
2. add i2c slave code
3. add i2c example code
4. add DRAM_ATTR for I2C array
bugfix: uart event mismatch
Fix bug of uart frame error and parity error interrupt mismatch in driver code, which will cause the corresponding interrupt can not be cleared correctly, and will finally cause a interrupt watch dog.
See merge request !335
GPIO driver: add per-pin interrupt handlers
1. add ISR handler apis so that users of different layers can hook their own isr handler on different GPIO.
Audio project has different software layers, they need different gpio isr handler for layer instead of processing all GPIO interrupts in one handler.
If this kind of calling a handler from isr is not proper, please kindly point out.
2. add gpio example code.
3. update gpio doc.
See merge request !345
1. add ISR handler apis so that users of different layers can hook their own isr handler on different GPIO.
Audio project has different software layers, they need different gpio isr handler for layer instead of processing all GPIO interrupts in one handler.
If this kind of calling a handler from isr is not proper, please kindly point out.
2. add gpio example code.
3. improve gpio.rst
4. add readme for gpio example
Squashed commits:
[278e50f] update: GPIO
1. coding style, add a space between conditional or loop keyword and an opening paren.
2. modify some return value and doc
3. use printf in example code
Squashed commits:
[efb23bb] minor change of comment
freertos: fix dual core issue
This commit try to fix dual issue tw9313 raised by QA
1. Put per-core data into critical session or interrupt disabled/enabled session
2. Idle task may have problem when it terminate the task in both core
See merge request !333
1. The transmitting mode of the packets from LWIP to MAC is changed from synchronous to asynchronous.
2. The receive buf mode : support pointer mode and copy mode.
3. Add get phy status func used to config mac register.
1. Fix bug of uart frame error and parity error interrupt mismatch in driver code, which will cause the corresponding interrupt can not be cleared correctly, and will finally cause a interrupt watch dog.
2. Add gpio pull-up for rx pin and cts pin.
This commit fixes:
1. xTaskGetCurrentTaskHandle may return wrong TCB when current task switch to a different core
2. Idle task may have problem when it terminate the task in both core
Minor fixes from various sources
- Fix memory debugging code. Noticed by Tuan.
- intr_enable/disable should be in IRAM. Noticed by rojer
- Still old timer code in examples in doxygen comments. Noticed on the forum by jumjum123
- Timer example was broken. Noticed on the forum by jumjum123
See merge request !325
ULP: add new instructions, fix bugs, add tests
This adds peripheral register read and write instructions, an instruction to wake the SoC from deep sleep, and some tests.
Also fixes two bugs: ANDI instruction definition, and running the ULP when in deep sleep mode.
See merge request !317
Fix exception handler to jump to correct vector instead of crashing to the double exception vector.
One-character fix... basically, this caused the exception handler to crash into the double-exception handler instead of nicy panic'ing.
See merge request !323
Secure boot: Option for app & partition table signing to happen outside build system
Allows for a remote signing server, private signing key does not need to be on the build system.
See merge request !320
Allow gw to be null
Github Pull Request 163: https://github.com/espressif/esp-idf/pull/163
Allow interfaces to be configured without a default gateway, for
local-only communication.
In case of the AP interface, if gw is not set, do not offer it.
See merge request !312
1. change all gatt cb function to 3 args and function type. add gattc_if/gatts_if as second argument
2. delete gatt_if of "gatt cb param"
3. separate conn_id and gatt_if from conn_id
4. change the demo code as the gatt changed
1. add sigma-delta code and example.
2. add gpio output signal in io matrix.
Squashed commits:
[a25e7d4] minor changes for doc
[6a03a1e] minor changes on comments and doc.
[97dd9e4] Add doc.
update index.rst
change example index
Starting the ULP using SENS_SAR_START_FORCE_REG doesn’t disable clock gating of RTC fast clock.
When SoC goes into deep sleep mode, RTC fast clock gets gated, so ULP can no longer run.
Instead, it has to be started using the timer (RTC_CNTL_ULP_CP_SLP_TIMER_EN bit).
When ULP is enabled by the timer, clock also gets enabled.
This change allows setting pin configuration for EXT1 wakeup depending on the state of RTC_PERIPH power domain:
- if peripherals are enabled (due to another wakeup mode, or due to esp_deep_sleep_pd_config call), we can keep internal pullups/pulldowns enabled
- if peripherals are disabled, pullups and pulldowns need to be disabled as well
Also add comments about the purpose of registers being configured.
This adds a workaround for a bug that following deep sleep wakeup, ISO (bus isolation) signal may be set for RTC fast memory.
We set FORCE_NOISO bit in RTC_CNTL_PWC_REG until we find out what is causing ISO signal to be set.
When ESP32 wakes up from deep sleep, flash is accessed an approximately 900us after power on.
Some flash chips need more time to become ready. This change adds a menuconfig option to add
some delay to the default deep sleep wake stub.
Fixes https://github.com/espressif/esp-idf/issues/117
This adds the following APIs to enable various wakeup sources:
- esp_deep_sleep_enable_timer_wakeup
- esp_deep_sleep_enable_ulp_wakeup
- esp_deep_sleep_enable_ext0_wakeup
- esp_deep_sleep_enable_ext1_wakeup
And an API to start deep sleep:
- esp_deep_sleep_start
1. TW8657, WIFI send the whole packet to smartconfig;
2. modify API annotation of smartconfig and sniffer;
3. export smartconfig APIs to programming guide;
